Abstract: A display device and a method of driving a display device are disclosed.

Abstract: A display device including a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel and having a precharge circuit configured to perform a precharging operation, and a timing controller configured to control the data driver, wherein the charge circuit generates a precharge voltage based on a precharge signal supplied in a horizontal blank period and is controlled to output or not output the precharge voltage based on a precharge selection signal.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and includes a shift register unit, a first clock signal line, and a second clock signal line in a peripheral region; a first portion and a second portion of a first connection wire of the display substrate are connected to a first gate electrode of a first control transistor of the shift register unit; an orthographic projection of the first portion on the base substrate is on a side of an orthographic projection of an active layer of the first control transistor on the base substrate away from a display region; and an orthographic projection of the second portion on the base substrate is on a side of the orthographic projection of the active layer of the first control transistor on the base substrate close to the display region.

Abstract: A pixel driving circuit, a display panel, and an electronic device. The pixel driving circuit includes: a pixel array including a plurality of pixel circuits, an RGBG pixel arrangement mode being adopted in the pixel array; at least four gate lines, arranged in a first direction of the pixel array, one row of pixel circuits being arranged between every two adjacent gate lines, and each row of pixel circuits corresponding to one gate line; at least eight data lines, arranged in a second direction perpendicular to the first direction and intersecting each gate line, each data line being connected to pixel circuits corresponding to sub-pixels of the same color in one column of pixel circuits; and a demultiplexer circuit, connected to the data lines, and configured to control the data lines to be in communication with an integrated circuit chip.

Abstract: A shift register includes: an input circuit configured to transmit an input signal received at an input signal terminal to a first node under control of a first clock signal transmitted by a first clock signal terminal; an output circuit configured to transmit a second clock signal received at a second clock signal terminal to an output signal terminal under control of a voltage of the first node; a first control circuit configured to, according to one of the second clock signal and a first voltage signal transmitted by a first voltage signal terminal, control a voltage of a second node under control of the voltage of the first node and the second clock signal; and a holding circuit configured to transmit the first voltage signal to the output signal terminal under control of the voltage of the second node.

Abstract: A display device includes: a cell matrix including a first cell line and a second cell line, wherein the first cell line includes first cells sharing first row lines, and the second cell line includes second cells sharing second row lines; a redundancy integrated circuit including a redundancy cell line including redundancy cells, wherein the redundancy cells share a third row line and are connected to the first and second cells through a plurality of column lines and a plurality of connection lines; and a display driver integrated circuit (DDI) configured to replace the first cell line or the second cell line with the redundancy cell line through the first row lines, the second row lines, and the third row line based on whether the first and second cell lines include a bad cell.

Abstract: Provided are a display substrate and a detection method therefor, and a display apparatus. Compensation sub-circuits that are in one-to-one correspondence with each stage of a shift register are arranged in a gate driving circuit, and a first capacitor in each compensation sub-circuit is thus charged under the control of a detection input circuit when each stage of the shift register outputs a signal stage by stage; and an output control circuit is used to disconnect the compensation sub-circuit from a pull-up node of the corresponding stage of the shift register. The triggering of each stage of the shift register is stopped after each stage of the shift register (CR(n)) completes outputting, and the output control circuit provides a signal of a first power voltage end to the pull-up node of the corresponding stage of the shift register under the control of a second control end and the first capacitor.

Abstract: A timing controller suitable for receiving image data and a timing signal from a host system and outputting output data to a data driving circuit may include a scrambler configured to output scrambled image data by scrambling the image data; a pattern detection unit configured to calculate a first unbalanced pattern count as a count of unbalanced patterns included in the image data and a second unbalanced pattern count as a count of unbalanced patterns included in the scrambled image data; and an output data determination unit configured to determine output data by using the first unbalanced pattern count and the second unbalanced pattern count.

Abstract: A display panel and a display device are provided. In an embodiment, the display panel has a display region and a non-display region and includes shift registers cascaded and arranged along a first direction. In an embodiment, the shift registers are located in the non-display region. In an embodiment, one of the shift registers includes a switch module and an output module. In an embodiment, the output module is coupled to an output terminal of the shift register and includes two output transistors, and the output transistors are located at a side of the switch module away from the display region. In this way, the probability of occurrence of abnormal phenomena, such as splash screen display, is reduced.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A display apparatus includes a display panel, a scan driver, a data driver and a timing controller. The display panel includes a plurality of pixels that are connected to a plurality of data lines and a plurality of scan lines having different lengths. The scan driver apply a plurality of scan signals to the plurality of scan lines. The data driver apply a plurality of data voltages to the plurality of data lines, and receive a plurality of sensing data that represent operating characteristics of all of the plurality of pixels from a plurality of sensing lines. The timing controller controls operations of the scan driver and the data driver, generates output image data considering the operating characteristics of all of the plurality of pixels and supply the output image data to the data drive.

Abstract: Provided are a display panel and a display device. The display panel includes a display region, a non-display region bordering two sides of the display region at least in a first direction and a hole-digging region. The distance from the hole-digging region to the non-display region on a first side of the display region is smaller than the distance from the hole-digging region to the non-display region on a second side of the display region. The display region includes pixel circuits and initialization signal lines. The non-display region includes cascaded initialization signal shift register units. The initialization signal shift register unit includes a first initialization signal shift register unit located in the non-display region on the first side of the display region. The first initialization signal shift register unit is electrically connected to a corresponding initialization signal line having a partial line segment extending around the hole-digging region.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an ith shift register is connected to a signal input terminal (INPUT) of a (i+p)th shift register, where (N?4)/2?p?N/2, and i is taken from 1 to (M?p); and a pull-up reset signal terminal of a jth shift register is connected to a signal output terminal (OUTPUT) of a (j+q)th shift register, where 1<q?p<N/2, and j is taken from 1 to (M?q).

Abstract: A special-shaped display panel includes: a special-shaped display area (S) having gate lines (G), some of the gate lines (G) being cut off in a non-display sub-area (S2) of the special-shaped display area (S); a first gate drive circuit set (A1) located on one side of the special-shaped display area (S), electrically connected to one ends of gate lines (G) which are not cut off by the non-display sub-area (S2), and electrically connected to gate lines (G) on one side which are cut off by the non-display sub-area (S2); and a second gate drive circuit set (A2) located on the other side of the special-shaped display area (S), electrically connected to the other ends of gate lines (G) which are not cut off by the non-display sub-area (S2), and electrically connected gate lines (G) on the other side which are cut off by the non-display sub-area (S2).

Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

Abstract: Provided are a gate driving circuit, a display substrate, a display device and a gate driving method, the gate driving circuit includes: a frequency doubling control circuit and an effective output circuit including first shift registers, the first shift register at the first stage has a first signal input terminal coupled with an output control signal line and a second signal input terminal coupled with the frequency doubling control circuit; the frequency doubling control circuit is coupled to the output control signal line, for providing a frequency doubling control signal thereto after a preset time period from the receipt of the output control signal in response to an output control signal from the output control signal line; the first shift register at the first stage outputs a scanning signal in response to the output control signal and a scanning signal in response to the frequency doubling control signal.

Abstract: A display device, which is a slidable display device, includes a display panel and a data driver. The display panel includes a first display area, a second display area that is in one of a taken-in position and a taken-out-of position of the display device, and a pad area located on one side of the first display area. The display panel includes pixels disposed in the first and second display areas, and is driven in a first mode in which an image is displayed in the first display area or a second mode in which an image is displayed in the first and second display areas. The data driver generates data voltages based on pixel data, outputs the data voltages to the pixels, and controls an order of the data voltages output in the second mode.

Abstract: A display device includes a display panel including pixels connected to scan lines and data lines, and connection line connected to the scan lines, and a scan driver which drives scan lines. The scan driver includes a scan signal output circuit which outputs a first output signal as a scan signal to a first output line and outputs a second output signal to a second output line, a signal distribution circuit which outputs the first output signal to a first or third connection line and outputs the second output signal to a second or fourth connection line in response to first and second distribution control signals, and a scan-off circuit which outputs gate-off level to at least one of the scan lines in response to first and second scan-off control signals.

Abstract: The present disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes a transistor, which includes a gate electrode, a gate insulating layer, an active layer, a first electrode and a second electrode; the first and second electrode are of comb-shaped structures; the first electrode includes first and second comb tooth portions arranged at intervals, and a first comb handle portion connecting the first and second comb tooth portions; and comb tooth electrodes of the first comb tooth portions have a different length from those of the second comb tooth portions; the second electrode includes third and fourth comb tooth portions arranged at intervals, and a second comb handle portion connecting the third and fourth comb tooth portions; the first and third comb tooth portions form an inter-digital structure, the second and fourth comb tooth portions form an inter-digital structure.

Abstract: The present disclosure provides a driving circuit, a driving method, a shift register and a display device. The drive circuit includes a first control circuit, a second control circuit, a first output circuit, a second output circuit and an output terminal; the first control circuit is configured to connect or disconnect the first node and the first control voltage terminal under the control of a control signal provided by the control terminal; the second control circuit is configured to connect or disconnect the second node and the second control voltage terminal under the control of the control signal.