Abstract: A gate driver on array (GOA) circuit and a display panel is provided. The GOA circuit includes a plurality of cascading GOA units. A current stage of the GOA units includes: a pull-up module, a pull-up control circuit unit, and a selection module. The pull-up module includes a first transistor. A source of the first transistor is connected to the selection module, a gate is connected to the pull-up control module through a first node, and a drain is configured to output a scan signal of the current stage. The selection module is configured to receive a first control signal and a second control signal to control the clock signal to transmit to the source of the first transistor.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.

Abstract: A charge sharing circuit, a charge sharing method, a display driving module and a display device are provided. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to first output control ends of two clock signal generation units, and configured to provide, when a first output module controls to not output a first voltage signal under the control of a first output control signal, an on control signal to the switch unit through a control signal output end. The switch unit is configured to control clock signal output ends of the two clock signal generation units to be electrically connected to each other under the control of the on control signal.

Abstract: A shift register includes: a first input sub-circuit configured to transmit a first clock signal to a first node in response to an input signal and a first voltage signal; a first output sub-circuit configured to transmit a second voltage signal to a first output signal terminal under control of a voltage of the first node; a second input sub-circuit configured to transmit the input signal to a second node in response to the first clock signal; and, a second output sub-circuit configured to transmit the first voltage signal to the first output signal terminal under control of a voltage of the second node. A voltage value of one of the first voltage signal and the second voltage signal is greater than that of a reference voltage, and a voltage value of another one is less than that of the reference voltage.

Abstract: An electronic communications method includes receiving, by a device, electronic information. The electronic communications method further includes receiving, by the device, additional electronic information. A time period between receiving the electronic information and the additional electronic information is less than another time period between receiving the electronic information and the additional electronic information by using a standard keyboard.

Abstract: There is disclosed a display driving device configured to drive a display device for displaying an image, including a source driver integrated circuit (IC) configured to convert image data into a source signal, and an energy harvesting device configured to convert thermal energy into electrical energy and supply the electrical energy to the source driver IC, wherein the energy harvesting device includes a thermal energy converter configured to convert thermal energy generated in the source driver IC to output an energy harvesting current, and an energy storage directly connected to the thermal energy converter, and configured to receive the energy harvesting current, store power, and output a first auxiliary voltage that is a voltage generated due to the stored power, wherein the thermal energy converter and the energy storage are located on the source driver IC.

Abstract: A shift register circuit (100) includes: an input circuit (110), a reset circuit (180), a first control circuit (120), a second control circuit (130), a third control circuit (140), a fourth control circuit (150), a fifth control circuit (160), a first output circuit (170a), a second output circuit (170b) and a third output circuit (170c). The shift register circuit (100) is configured to be capable of providing three different output signals as three different gate driving signals required to drive a pixel array of a display panel (810).

Abstract: A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.

Abstract: Provided are a display panel and a display device. The display panel includes a driving circuit. The driving circuit includes N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, and a third control unit. The first control unit is configured to receive a third voltage signal and control a signal of a fourth node in response to a frequency control signal. The second control unit is configured to receive a fourth voltage signal and control a signal of a fifth node in response to the frequency control signal. The third control unit is configured to receive a fifth voltage signal and generate an output signal in response to a signal of the fourth node; or the third control unit is configured to receive a sixth voltage signal and generate an output signal in response to a signal of the fifth node.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. Each shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive a signal of a preset node and a first output control signal and control a signal of a fourth node, where the preset node is one of a second node or a third node. A first output control signal received by a shift register at an M1-th stage is a signal of the preset node of a shift register at an M2-th stage, where 1?M1?N, 1?M2?N, 1?|M1?M2|?i, and 2?i?N?1.

Abstract: A driving circuit includes at least two shift registers in cascade. In each shift register, a first output control module is configured to transmit a voltage of a first voltage terminal to an output terminal in response to a turn-on level of a first node. A second output control module is configured to transmit a voltage of a second voltage terminal to an output terminal in response to a turn-on level of a second node. A first node control module is configured to transmit a voltage of the input terminal to the first node in response to a turn-on level of a first clock signal terminal and transmit a voltage of the second voltage terminal to the first node in response to turn-on levels of the second clock signal terminal and the third node or in response to the turn-on level of the second node.

Abstract: A light control panel including an image display region including a region corresponding to an image display region in a display panel and a region corresponding to a peripheral circuit region in the display panel is provided between the display panel and a backlight. A pattern image for controlling radiation of light emitted from the backlight to the display panel is displayed in the image display region in the light control panel according to an action state of the peripheral circuit in the display panel.

Abstract: Provided are a display panel and a display device. The display panel includes multiple cascaded gate drive units. Each gate drive unit includes a shift register unit and an inverted unit. The inverted unit is electrically connected to the shift register unit. A scan output terminal of the shift register unit is electrically connected to one scan line. An inverted scan output terminal of the inverted unit is electrically connected to one inverted scan line. The scan output terminal of the shift register unit outputs a first effective pulse signal. The inverted scan output terminal of the inverted unit outputs a second effective pulse signal. A time period corresponding to the first effective pulse signal at least partially overlaps a time period corresponding to the second effective pulse signal, and the type of the first effective pulse signal is opposite to the type of the second effective pulse signal.

Abstract: A display device includes: a base substrate; a light emitting element located on the base substrate; a thin-film encapsulation layer located on the light emitting element; touch electrodes located on the thin-film encapsulation layer, each of the touch electrode including an opening; and a strain gauge including: resistance lines located in the openings, respectively, the resistance lines located in the same layer as the touch electrodes and having variable resistance values changed in response to a touch input; a first connection line connecting two resistance lines neighboring each other along a first direction; and a second connection line connecting two resistance lines neighboring each other along a second direction, the second direction intersecting the first direction, wherein the first connection line and the second connection line are located between the thin-film encapsulation layer and the resistance lines.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel, having a display region and a frame region outside the display region, includes a base substrate; a buffer layer on a side of the base substrate, where the buffer layer includes an a-Si layer; a semiconductor layer on a side of the buffer layer away from the base substrate; an insulation layer on a side of the semiconductor layer away from the base substrate; and a power signal layer on a side of the insulation layer away from the base substrate. The power signal layer includes a plurality of first power voltage lines in the display region; and the power signal layer is electrically connected to a power signal terminal which alternately outputs a positive voltage signal and a negative voltage signal.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal under control of the level of the first node; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.

Abstract: An electronic device includes a display panel, an integrated circuit and a connection line. The display panel includes a first substrate, a second substrate, a display component and a sensing unit, the second substrate is opposite to the first substrate, the display component is disposed on an inner surface of the first substrate, and the sensing unit is disposed on an inner surface the second substrate. The integrated circuit is for driving the display component and the sensing unit. The connection line is disposed on a side surface of the second substrate. The sensing unit is electrically connected with the integrated circuit through the connection line.

Abstract: A display driver is provided. A designation of an output timing at each of first and kth output channels is received, and first and second delay pulse signals are generated at respective output timings of the first and the kth output channels. First to kth first direction delay shift signals where a first delay pulse signal is present after a delay increased for each output channel from the first toward the kth output channel are generated. First to kth second direction delay shift signals where a second delay pulse signal is present after the delay increased for each output channel from the kth toward the first output channel are generated. One whose timing at which a delay pulse signal is present is earlier is selected from each of the direction delay shift signals corresponding to the same output channel, and set as first to kth output timing signals.

Abstract: Provided is a spatial light modulator device that includes a light modulation unit, a first memory, and a second memory. The light modulation unit performs a transition operation between a first state and a second state. In the first memory, data for specifying which one state of the first state and the second state the light modulation unit is to be put in is written during a transition time in which the transition operation is performed. In the second memory, the data retained in the first memory is written after the transition time ends and the second memory supplies the data to the light modulation unit.

Abstract: An electronic apparatus includes a processing unit, a memory, a processor, and an operation control unit. The processing unit executes system processing based on a system. The memory temporarily stores image data of an image captured by an imaging device. The processor processes image data stored in the memory. The operation control unit controls an operating state of the system. The processor includes a face detection unit that processes image data of an image obtained by the imaging device capturing a predetermined imaging range and stored in the memory to perform detection of a face area with a face captured therein and an orientation of the face from the image. The operation control unit controls, according to a detection result by the face detection unit, the operating state of the system to be a first operating state or a second operating state.