Abstract: The present disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes a transistor, which includes a gate electrode, a gate insulating layer, an active layer, a first electrode and a second electrode; the first and second electrode are of comb-shaped structures; the first electrode includes first and second comb tooth portions arranged at intervals, and a first comb handle portion connecting the first and second comb tooth portions; and comb tooth electrodes of the first comb tooth portions have a different length from those of the second comb tooth portions; the second electrode includes third and fourth comb tooth portions arranged at intervals, and a second comb handle portion connecting the third and fourth comb tooth portions; the first and third comb tooth portions form an inter-digital structure, the second and fourth comb tooth portions form an inter-digital structure.

Abstract: The present disclosure provides a driving circuit, a driving method, a shift register and a display device. The drive circuit includes a first control circuit, a second control circuit, a first output circuit, a second output circuit and an output terminal; the first control circuit is configured to connect or disconnect the first node and the first control voltage terminal under the control of a control signal provided by the control terminal; the second control circuit is configured to connect or disconnect the second node and the second control voltage terminal under the control of the control signal.

Abstract: A gate driver and a display device including the gate driver are discussed. The gate driver in one example includes a shift register configured to control charging and discharging of a Q node and a QB node, and i output buffers sequentially connected to the shift register, where i is a natural number of at least 2. Each output buffer is configured to output a gate signal to a corresponding gate line in response to a voltage of the Q node and a voltage of the QB node. The gate driver further includes a dummy output buffer connected to the last stage of the shift register and configured to output a dummy signal to a dummy line in response to the voltage of the Q node.

Abstract: A display device including: first pixels connected to a first write line and a first compensation line; second pixels connected to a second write fine and a second compensation line; third pixels connected to a third write line and a third compensation line; fourth pixels connected to a fourth write line and a fourth compensation line; fifth pixels connected to a fifth write line and a fifth compensation line; sixth pixels connected to a sixth write line and a sixth compensation line; seventh pixels connected to a seventh write line and a seventh compensation line; and eighth pixels connected to an eighth write line and an eighth compensation line, the first to fourth compensation lines are connected to a first node, the fifth and sixth compensation lines are connected to a second node, the seventh and eighth compensation lines are connected to a third node.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.

Abstract: An electronic device is provided. The electronic device includes a first housing including a first face and a second face, a second housing including a third face and a fourth face, a folding part rotatably connecting the first housing and the second housing, a flexible display disposed on the first face and the third face, a camera exposed through at least a portion of the fourth face, a memory configured to store instructions, and a processor configured to determine an orientation of the electronic device and a direction in which the camera is pointed while a camera application is executed, identify the first area or the second area as an area in which a preview image acquired through the camera is displayed based at least on the determined direction and the determined orientation, and display the preview image, acquired through the camera, in the identified area using the flexible display.

Abstract: A display device includes a display control circuit. The display control circuit includes: an arithmetic unit obtaining a video signal, and calculating, in accordance with the video signal, an average voltage value of a source signal in a display period; and a controller and a signal synthesizer supplying, in the display period, a source signal, based on the video signal, from a source drive circuit to a plurality of source lines, and supplying, in a suspension period, a source signal, having the average voltage value, from a source drive circuit to each of the source lines.

Abstract: A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Abstract: The present disclosure relates to the field of display technology, and in particular, to a gate driving structure, an array substrate and a display device. The gate driving structure may include: a base substrate; a shift register, formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group, formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.

Abstract: A source driver includes a plurality of shift register groups cascaded in sequence, an enable control circuit and at least one switching circuit electrically connected to the enable control circuit. Each shift register group includes a plurality of stages of shift registers, and is configured to sample digitized image data; a first start signal of an n-th shift register group is output by an (n?1)-th shift register group, n is a positive integer greater than 2. The enable control circuit is configured to output a first turn-on signal or a first turn-off signal. In two adjacent shift register groups, a last-stage shift register in a present shift register group is electrically connected to a first-stage shift register in a next shift register group through a switching circuit.

Abstract: A display panel, a driving method of a display panel, and a display device are provided. The display panel includes pixel circuits and a gate driving circuit including cascaded first shift register units. A trigger signal input terminal of the first stage first shift register unit is connected to a trigger signal terminal through a first switch element. A signal output terminal of the i-th stage first shift register unit is connected to a trigger signal input terminal of the (i+1)-th stage first shift register unit through a second switch element. A trigger signal input terminal of the N-th stage first shift register unit is connected to the trigger signal terminal through a third switch element. A signal output terminal of the j-th stage first shift register unit is connected to a trigger signal input terminal of the (j?1)-th stage first shift register unit through a fourth switch element.

Abstract: A pixel driving circuit includes a driving control sub-circuit and a time control sub-circuit. The driving control sub-circuit includes a first driving sub-circuit. The first driving sub-circuit is configured to output a driving signal to drive an element to be driven to operate. The time control sub-circuit includes a second driving sub-circuit. The second driving sub-circuit is configured to output a third voltage signal to make the first driving sub-circuit stop outputting the driving signal, so as to control operating duration of the element to be driven.

Abstract: Provided is a display substrate. The display substrate includes a base substrate, a plurality of gate lines, a plurality of data lines, and a plurality of rows of pixels arranged in an array on the base substrate, and a plurality of shift circuits disposed on the base substrate, wherein in a plurality of pixels connected to each shift circuit, the respective pixels sharing the same data line have the same color, and each shift circuit is connected to one turn-on signal terminal.

Abstract: A display device includes a plurality of pixels connected to a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines, where the pixels are arranged in a plurality of rows, a plurality of first stages connected to the first scan lines, a plurality of second stages connected to the second scan lines, and a data driver connected to the data lines. Each of the first scan lines is connected to pixels arranged in a corresponding row among the rows. Each of the second scan lines is commonly connected to pixels arranged in corresponding 8h rows among the plurality of rows, where h is a natural number.

Abstract: Disclosed is a display device having touch sensors which may improve visibility. In the display device, the touch sensors having a multilayer structure including a blackened layer are arranged on an encapsulation assembly arranged to cover light emitting elements, and touch pads having a multilayer structure including a partially transparent conductive layer are arranged on a region of a substrate exposed by the encapsulation assembly. Therefore, the blackened layer may prevent reflection of external light and thus visibility may be improved, and the partially transparent conductive layer may lower sheet resistance of the touch pads and thus contact resistance between the touch pads and a driver integrated circuit may be reduced.

Abstract: Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q? node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q? node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

Abstract: A system and/or method that uses a body posture of a user to determine and modulate a content mode of a virtual reality system. The content mode may define the manner in which virtual reality content is presented to the user and/or the manner in which the user interacts with the virtual reality content. The user's body posture and/or a change in body posture may cause the content mode and/or the virtual reality content to change accordingly. In some implementations, primary content may be presented to the user according to a first content mode in response to the user sitting. Secondary virtual reality content may be presented to the user according to the second content mode in response to the user standing. As such, a user may initiate a change in the virtual reality content and/or the content mode by standing from a sitting posture and/or sitting from a standing posture.

Abstract: A gate driver on array (GOA) circuit and a display panel is provided. The GOA circuit includes a plurality of cascading GOA units. A current stage of the GOA units includes: a pull-up module, a pull-up control circuit unit, and a selection module. The pull-up module includes a first transistor. A source of the first transistor is connected to the selection module, a gate is connected to the pull-up control module through a first node, and a drain is configured to output a scan signal of the current stage. The selection module is configured to receive a first control signal and a second control signal to control the clock signal to transmit to the source of the first transistor.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.

Abstract: A charge sharing circuit, a charge sharing method, a display driving module and a display device are provided. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to first output control ends of two clock signal generation units, and configured to provide, when a first output module controls to not output a first voltage signal under the control of a first output control signal, an on control signal to the switch unit through a control signal output end. The switch unit is configured to control clock signal output ends of the two clock signal generation units to be electrically connected to each other under the control of the on control signal.