Abstract: A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.

Abstract: Provided are a method, system, and program for processing packets from an Input/Output (I/O) device. Information is maintained indicating a first buffer and second buffer for use with each descriptor, wherein one of the first and second buffers is assigned to the descriptor used by the I/O device, and wherein the I/O device write packets to the buffers assigned to the descriptors. The first buffer including a packet from the I/O device is accessed, wherein the accessed first buffer is assigned to an accessed descriptor. The packet in the accessed first buffer is processed and if the second buffer assigned to the accessed descriptor is available, then information for the accessed descriptor is updated to indicate that the second buffer is assigned to the accessed descriptor before completing the processing of the packet in the first buffer.

Abstract: Each attention button is tied to a presence signal, which is also used to detect the presence of a PCI adapter card within a slot. By comparing HPPC register states, pending due to a system control interrupt (“SCI”), with stored HPPC register states prior to the SCI, the HPPC is able to distinguish between an attention button press and a PCI card insertion or removal and therefore may respond appropriately to the SCI. According to the method, SCIs generated in a computer system by attention buttons are diagnosed and serviced by storing the contents of the HPPC registers. The contents of the registers identify the state of the presence and manually-operated retention latch (“MRL”) signals prior to the occurrence of a SCI and upon receiving a SCI corresponding to a state change for either signal, identify the hot plug controller and the slot where the interrupt occurred.

Abstract: A computer-implemented method and system are provided for supporting hardware devices that are connected to the computer via a network. The existence of any hardware device connected on the network is detected in the method. Information descriptive of the connected device is then obtained, either from the device or from the user. Based upon the obtained information, a logical representation of the connected device is created. The driver for the detected device is then located and installed. From this point on, the network-connected hardware device appears to the computer in the same manner as a locally connected hardware device.

Abstract: A network is configured to apply power and data signals to networked devices for operation of the devices. A backup power supply module is coupled to the source of network power and to a secondary power source. The secondary power source may have an adjustable voltage level or a level fixed with relation to the network power voltage level. In the event of a loss or insufficiency of network power, power from the secondary source is automatically applied to the connected device or devices. The device may be programmed for certain failure modes and the secondary power source provides the power needed for operation in the event of loss of network power.

Abstract: A designated byte of a PS/2 packet is used for data not recognized by a conventional PS/2 port driver. Each packet byte received by the conventional port driver is read by an Interrupt Service Routine (ISR) of a filter driver. If a received packet contains an unrecognized data type, that data is extracted. The filter driver converts the byte containing the data to 0000 0000. The port driver provides the all-zero byte to a higher level driver for processing into a subsequent data structure. A Service Callback Routine of the filter driver receives that data structure from the higher level driver. Depending upon the type of unrecognized data extracted by the ISR, that data is then either inserted into the data structure or passed independently of that data structure to a user level application.

Abstract: A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one second register is provided for communicating a current port buffer size and one second register is associated with each physical port of the channel adapter. A plurality of third registers is provided for communicating a current VL buffer size, and one third register is associated with each VL of each physical port of the channel adapter. The second register is used for receiving change requests for adjusting the current port buffer size for an associated physical port. The third register is used for receiving change requests for adjusting the current VL buffer size for an associated VL.

Abstract: Methods and systems are provided for enabling a network between a first and a second processor using at least one additional processor separate from the first and second processors. In one embodiment, the at least one additional processor receives information indicating a consent on behalf of the first processor to enabling a tunnel between the first processor and the second processor and receives information indicating a consent on behalf of the second processor to enabling a tunnel between the second processor and the first processor. The at least one additional processor determines a first virtual address for the first processor and a second virtual address for the second processor such that the first and second virtual addresses uniquely identify the first and second processors, respectively, and are routable through the network.

Abstract: Methods and systems are provided for providing network services using at least one processor, such as a network operations center that interfaces a base network. The network operations center may receive information identifying a user authorized to administer a first processor, which may be separate from the network operations center, and a base address that is routable in the base network. The network operations center may provide through the base network code and information for self-configuring the first processor as a gateway that interfaces the base network at the base address. The first processor may execute the provided code to self-configure itself as the gateway based on the provided information.

Abstract: The present invention relates to a computer-implemented method that includes receiving a sequence of input values. Furthermore, the method includes determining if the sequence of input values is a manual input or an automated input.

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

Abstract: Circuit board having a plurality of bus lines (6), which run on the circuit board (1) essentially parallel to a preferred direction of the circuit board (1), and having at least one integrated circuit (3) for the high-speed data processing of data, which integrated circuit is arranged on the circuit board (1), is integrated in a housing (4) having a plurality of housing sides (5) and has a plurality of parallel interfaces for connection to the bus lines (6), in which case the housing sides (5) of the integrated circuits (3) are oriented at an inclination with respect to the preferred direction of the circuit board (2).

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.

Abstract: A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.

Abstract: A controller chip for coupling a computer system with a flash storage system is disclosed. The controller chip comprises an interface mechanism for determining whether the Flash storage system includes a controller and an adapter for providing the appropriate interface to the computer system to allow the computer system to communicate with the Flash storage system. In a preferred embodiment, the flash storage system comprising at least a portion of a medium ID section; and a flash section, wherein the medium ID section contains specifications of the medium ID. Through the use of this system a plurality of different adapters and a flash storage system can be managed while utilizing the same hardware components.

Abstract: A dynamic network interface is described, intended to enable the efficient processing of received data within a computer network by a target computer system by reducing excessive copying of the received data prior to being accessed by a network software application.

Abstract: An enhanced VPD structure includes a type field to indicate whether a particular property is a general property to be associated with an interface card or other computer system component, or a device- or function-specific property to be associated with one or more devices or functions. The enhanced VPD structure also includes fields for identifying the device(s) and/or function(s) to which a device- or function-specific property applies, along with the value of the property, a data type and length of the property, and a meaningful name of the property. The enhanced VPD structure may be accessed during system boot, during hot-swapping of an interface card or other component, or at other times.

Abstract: An address is obtained for storing data that is to be output with a peripheral device, as well as information for formatting the data to be compatible for being output by the peripheral device. A data file is written to a storage area at the address that has data that is formatted to be compatible for being output by the peripheral device.

Abstract: In an environment employing a fabric, such as a cascading switch network, a predictable input/output (I/O) configuration is provided. The I/O configuration explicitly specifies the one or more peripheral units accessible by a program, such as an operating system. Other peripheral units not specified in the I/O configuration are not accessible, thus, providing a secure environment.

Abstract: Improved techniques for rendering a peripheral device removable (e.g., unpluggable) are disclosed. According to one aspect of the invention, the peripheral device is rendered removable from a host computer without preparatory user actions. In effect, the peripheral device can be automatically prepared for removal in the event that its user removes (unplugs) it from its host computer. According to another aspect of the invention, the peripheral device includes a data storage device that is mounted to a file system of the other computer when the other computer desires access to the data storage device. Otherwise, the data storage device is normally unmounted so that if the peripheral device were to be removed (e.g., unplugged) no harm or damage to data stored therein would occur. These aspects of the invention can be utilized alone or in combination with one another.