Abstract: The present invention allows program specific configuration of several physical or logical readers, or other I/O devices, by using a configuration tool and a reader access layer. In an example embodiment, a configuration tool allows, a specifying access rights and priority rights for each single reader in conjunction with each single program. A reader access layer communicates with each program directly, calls up the reader access list for the requesting program, checks the access rights and the priority order for the available readers and returns a response to the requesting program containing information for accessing the active reader with the highest available priority. It secures previously defined access rights and access priorities between readers and programs defined in the reader access list remain unchanged independently when new readers are added.

Abstract: In the method, a logical unity is queried with a first command requesting first identifier data, to determine whether a unique identifier (UID) for the logical unit can be constructed based on the first identifier data. If a UID cannot be constructed from the first identifier data, the logical unit is queried with a second command requesting second identifier data, to determined if a UID can be constructed based on the second identifier data. If a UID cannot be constructed based on the second identifier data, the logical unit is queried with a third command requesting third identifier data. Information is extracted from the first identifier data and from the third identifier data and a UID is generated based on the extracted information.

Abstract: A peripheral data storage subsystem is for use with a computer system. The computer system has a host PCI bus and a serial PCI host bus adapter coupled to the host PCI bus. The peripheral data storage subsystem includes a plurality of data storage devices and a data storage device to parallel PCI interface that is coupled to each of the data storage devices, a parallel PCI to serial PCI interface coupled to the data storage device to parallel PCI interface and a serial PCI link interconnect. The serial PCI link-interconnect couples the parallel PCI to serial PCI interface of the peripheral data storage subsystem to the serial PCI host bus adapter of the computer system.

Abstract: The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in the buffer device a plurality of buffer segments. Respective ones of the buffer segments are filled with data from at least one data source device operating in a respective clock domain. Upon any respective buffer segment being filled up, the method allows to generate an indication of availability of the contents of the respective buffer segment to at least one data destination device operating in a respective clock domain. The clock domain of the at least one source device is distinct than the clock domain of the at least one destination device.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g.

Abstract: A system with a set of modules having synchronized timing. The synchronized timing of the modules enables precise coordination of measurements and stimuli for an arbitrary number of modules. The modules communicate and maintain time synchronization using a communication mechanism that may be adapted to localized positioning of modules and/or widely dispersed positioning of modules with no change to the underlying functionality in the modules.

Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.

Abstract: An embedded controller includes a central processing unit, a memory interface for interface with an external memory, and a function block or peripheral device with a register for storing operation state information. The peripheral device includes a detection circuit, a storage unit, for example in the form of a FIFO, a multiplexer, and a direct memory access (DMA) controller. The state detection circuit activates a flag signal whenever the operation state information of the register is varied, and the FIFO stores the operation state information from the register in response to the flag signal. The multiplexer is controlled by the DMA controller and transmits the operation state information of the FIFO to an internal bus. As a result, the operation state information of the FIFO is stored in the external memory through the memory interface.

Abstract: A power off method for a wireless device is proposed. A battery is installed in the wireless device as the power supply. When the power source is connected to the wireless device, an identification process is conducted between the wireless device and the wireless receiver connected to a computer. After the completion of successful identification process, the control chip within the wireless device stores a set of ID code that can be identified by the wireless receiver. In order to prevent wireless devices from being inadvertently reactivated, these devices are usually turned off during traveling. The present invention provides a power off method that terminates power to all parts of the wireless device except the control chip by a certain operation on the connect button. Therefore, an individual power switch is not required while the device can be turned off, and resume the normal operation on the next power on.

Abstract: An external interface for a microprocessor system uses a programmed configuration bit to establish the functionality of a computer port, which improves external interface data transfer speed and input/output power consumption. In particular, the configuration bit allows the microprocessor user to establish the computer port as a memory port, input/output port or the like. The configuration bit is provided to the computer port at system power up or reset. Moreover, the configuration bit may be stored in flash memory and provided to the microprocessor computer port or, in the alternative, the configuration bit may be provided to the computer port directly via the microprocessor bus interface.

Abstract: A method of virtualizing hardware resources in a multiprocessor computing environment is provided. Each resource is provided a resource address. A hardware resource map is provided to store virtual resource addresses and physical resource addresses. Remapping hardware is utilized to redirect virtual addresses to physical addresses. The method of virtualizing hardware resources may be applied to any resource mapped across the bus, including memory address space, and I/O address space. Accordingly, the method of virtualizing hardware resources through platform firmware enables dynamic routing of resource accesses during run-time.

Abstract: A head unit outputs a control bus command in response to an input operation by a user. A conversion unit converts the control bus command into a USB data frame and outputs the USB data frame to a notebook personal computer. Based on the USB data frame, and notebook personal computer reads music data stored in a hard disk drive, and outputs the music data to the head unit via the conversion unit. If the music data is compressed, the music data is decoded at the notebook personal computer. Thus, a dedicated decoding LSI need not be provided in the head unit.

Abstract: The present invention includes a housing for carrying the components or circuits. The housing include a first part that is located in the slot when the present invention is inserted into the computer. The second part of the housing extends outside the slot of the computer. A wireless transmission module is set in the second part for transmitting the signal. A SIM is set also in the second part of the housing. A hot swapping protector is located in the first part of the housing and electrically coupled to the SIM for protection. A card reader is connected to the hot swapping protector and a power control module is connected to the card reader, the hot swapping protector for providing the power.

Abstract: An optical disk drive control apparatus, which enables the operation of the optical disk drive during the power-off state or a power-saving mode (low-power suspend mode), is provided. The notebook computer comprises an other-function chip with idle pins. The idle pins are connected to the optical disk drive via signal lines to control the operation of the optical disk drive. Moreover, in order to detect control signals transmitted from the other-function chip, a signal-processing device can be used to converting the control signals to be compliant with the ATAPI standard. Alternative ways, like setting up a protocol for the other-function chip and the optical disk drive and table lookup, also enable the control signals from the standard interface to be detected without an additional signal transformation procedure.

Abstract: A hand-held device having a display and a browser application which supports functionality particularly suited for the hand-held device. For example, the browser application supports a full screen tag which allows information to be displayed as a full screen within the display. The browser application may also support a tag for use in displaying a link the activation of which will cause the hand-held device to transmit command codes to a consumer appliance. Still further, the browser application can support a tag which the hand-held device can use to issue reminders.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: Methods and associated structure operable within a SCSI-based storage subsystem to adapt the storage controller for use with non-SCSI disk drives. A firmware layer of the present invention intercepts SCSI read/write requests and pass through command blocks (CDBs) generated by the storage management core of the controller and translates the requests and command structures into corresponding command structures for transmission to a non-SCSI disk drive. In like manner, the firmware layer of the present invention receives status information from non-SCSI disk drives and translates the status information into corresponding SCSI compatible status information. In one exemplary preferred embodiment, a storage subsystem designed for interaction with SCSI disk drives may be adapted in accordance with the present invention to utilize lower-cost, commodity disk drives such as IDE compatible disk drives.

Abstract: Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.

Abstract: A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial controller. The SVP writes data to be transmitted to the node from the I/O unit into the serial controller. The node reads data stored in the serial controller. The node also writes data to be transmitted to the I/O unit into the serial controller. The serial controller instructs the SVP to read the data written by the node. The SVP reads this data and sends it to the I/O unit.