Abstract: A system and method for upgrading data transmission performance under programmed input/output (PIO) mode is disclosed. In one embodiment, a PIO accelerating device is established in an IDE controller for handling data transmissions concerned with read/write operations after taking over associated control right from processing unit. A counter is configured in the PIO accelerating device for varying its stored content followed by a predetermined sequence in responsive to the input pulses of a system clock. A timing signal generator is also established in the PIO accelerating device for issuing signals directed to the IDE device and the buffer in the IDE controller for activating associated data transmission operations while the stored content reaches to a predetermined threshold. Optimal performance to data transmission under IO mode 4 of the PIO mode can be achieved by employing the disclosed hardware configuration.

Abstract: A reconfigurable flash media reader system provides a flash media reader that accepts both asynchronous and synchronous flash media cards. The reader identifies the card type of the inserted flash media card and notifies the host computer of the card type. The host computer has a list of interface information for different types of flash media cards and references the card type in the list and sets the proper baud rate on the reader. If the flash media card is a synchronous card, data that is to written into the flash media card is gathered and converted to the proper card IO strobes for the card type which are interleaved with the proper card clock strobes for the card type into a bit stream in a bulk transfer packet. The reader extracts the data bit stream from said bulk transfer packet and clocks the data bit stream into the flash media card using the baud rate as a reference clock.

Abstract: This method of managing the resources of a computer communication means for processing a computer document stored on a processing control device connected by the communication means to at least one processing device includes a step of selecting at least one processing device of the communication means as a function of a first group of criteria relating to the functioning of this device, and a second group of criteria relating to its geographical situation.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: Briefly, the present invention provides a system and method for distributing SCSI semantics throughout a network. Specifically, the present invention distributes the SCSI semantics through multiple parallel agents and a separate controller. This configuration allows performance-sensitive distribution of SCSI semantics to be parallelized and optimized for performance in the agents, while the control and management of the SCSI semantics is centralized in the controller chosen for optimal cost, management, and other implementation practicalities. In this design, the SCSI semantics are stored in the controller, and portions of the SCSI semantics are distributed to the mapping agents as cached, read-only information. The controller is responsible for persistent storage of the SCSI semantics, thereby consolidating the costs and management for the SCSI semantics in a single component.

Abstract: A system, method, apparatus, and computer program code for delivering a treatment includes generating a personal area network associated with a patient, said personal area network transmitting a patient identifier associated with said patient, retrieving treatment data associated with said patient identifier, and operating a treatment device pursuant to said treatment data.

Abstract: A system and methods are shown for generating a transport stream. An application reads a transport stream file stored in memory. The application provides access to the transport stream file to a graphics card using a multimedia peripheral port (MPP). The MPP is used to provide data from the transport stream file to a transport stream demultiplexer. The application determines a desired transmission rate from the data present between program clock references in the transport stream file. The application suspends transmissions to the transport stream demultiplexer to allow a transmission bit-rate to match the desired bit-rate. The application also suspends transmission when the receiving transport demultiplexer determines its buffers are nearly full.

Abstract: A signal from a remote control is used to operate a device having a built-in communication port and a built-in microprocessor, even though the port does not normally recognize the signal. Specifically, even if the port flags an error during decoding of information from the remote control signal, the microprocessor ignores the error and uses the decoded information in the normal manner. Therefore, the microprocessor recognizes a pattern formed at the communication port by a signal emitted by the remote control, e.g. to identify a button on the remote control that has been pressed. During the recognition process, the port flags one or more errors (such as framing error, parity error), and such errors are ignored by the microprocessor. Programming the microprocessor to ignore errors from the port allows the device to operate with signals in a format different from the format normally recognized by the port.

Abstract: An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.

Abstract: A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.

Abstract: A data storage and processing device is reversibly attachable to a selected member of a set of appliances. The device includes a data storage medium and a processor. Each appliance includes appropriate functional components, a power source and a user interface. The device receives power from the attached appliance. Commands for operating the attached appliance are stored in the data storage medium and are executed by the processor in response to user instructions received from the attached appliance in order to operate the functional components. Preferably, the device receives power only from the attached appliance, and the functional components are operated, in response to the user instructions, only by the device's processor.

Abstract: A method for identifying Serial Peripheral Interface (SPI) compatible serial interface memory devices. A microprocessor sends a single command requesting identification information to an SPI device installed on the SPI bus. A byte string, including the JEDEC manufacturer ID, device ID, and any extended device information, is sent back to the microprocessor. The byte string may include one or more continuation codes when the manufacturer ID exceeds 1 byte. The byte string also includes one byte indicating how many bytes of extended device information should be read by the microprocessor. The identification process, issuing the command and receiving the reply, is completed in one operation.

Abstract: The present invention provides a reliable and high-speed data transfer method that achieves a high transfer efficiency and a high application processing efficiency concurrently and a disk control unit (disk controller) using such a method. In reliable data transfer in which, when data is transferred from an initiator to a target, the data received by the target is checked for validity by using an error check code attached to the data, a transfer status indicating whether the data is valid is returned from the target to the initiator, and, if a transfer error occurring during the data transfer is detected by the transfer status, the initiator retries to transfer the data to the target, a data transfer method for logical records that are units of data transfer between the initiator and the target is disclosed.

Abstract: Enabled is operation, including confirmation of the data content of a PC card on a display screen or outputting the data onto an output unit, according to the operation of another terminal unit connected to a network. A module to be removably inserted by a PC card and an output unit for displaying and printing input data are connected through an interface. The module and a terminal unit are connected for data transmission and reception through a communicating unit for communicating data on a predetermined communication protocol. By inserting the PC card in the module, the data of the PC card is converted into a data form to be data-processed on the output unit and into a data form suited for a communication protocol of the communicating unit.

Abstract: A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are designated cache only. Cache only commands are added to the queue only if they can be completed without accessing the disk I/O subsystem. If the disk I/O subsystem would be accessed in order to complete a cache only command, the command is returned to the operating system with an error. The operating system can then add the command to an operating system or back-up queue.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

Abstract: A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.