Abstract: Data is transmitted in a signal comprising a data signal D.sub.m at a frequency within a range B of discrete frequency tones D.sub.0 to D.sub.m-1 representing a predetermined range of digital values, and a pilot signal (36, 37). The signal is received by a circuit comprising a transformer (44 to 54) which transforms the received signal into a set of frequency samples of the pilot signal and a set of frequency samples of the data signal. The samples are input to a correlator (58) which correlates the set of frequency samples of the pilot signal with the set of frequency samples of the data signal at each of the discrete frequency tones in order to identify the discrete frequency tone to which the frequency of the data signal corresponds. In this way, the digital value represented by the data signal can be identified. The circuit is suitable for use in a radio pager for receiving data signal transmissions from a distant source which may be transmitted from a satellite.

Abstract: A service clock regenerator regenerates a local clock from time stamps of a remote clock transmitted over a network by determining the slope of (or difference between current and previous) time stamps of the remote clock and the slope of time stamps of the local clock. A phase difference is formed as the difference between the slope of the time stamps of the remote clock and the slope of the time stamps of the local clock and this phase difference is accumulated to generate a phase error signal. The phase error signal is filtered to generate a frequency adjustment signal having a magnitude that depends on the phase error signal. The frequency of the local clock is adjusted according to the magnitude of the frequency adjustment signal thereby reducing a phase difference between the remote time stamps and the local time stamps.

Abstract: A line card integrates subscriber line interface circuitry, A/D and D/A converters, and digital signal processing technology. The digital signal processing technology performs many line card tasks such as switch hook detection, ground key detection, DC feed control, polarity reversal, ringing tests, fault detection, power cross detection, and ring trip detection. Silent polarity reversal is achieved by modulating a digital DC feed current waveform in accordance with a programmable predetermined waveform to smoothly transition the DC voltage of subscriber loop conductors A and B between approximately ground and central office battery voltage. The modulated waveform includes little if any energy in audio frequencies. Additionally, the functionality of the line cards 308[m:1] may be implemented partially or completely in hardware of software.

Abstract: The present invention provides a method of generating a signal that may be used to determine the characteristic response of a communication channel that utilizes the public Digital Telephone Network (DTN). The channel includes the DTN, which may have Network Digital Attenuators (NDA) and/or Robbed Bit Signalling (RBS), and a Digital-to-Analog Converter (DAC), (also known as a codec), as well as the analog characteristics of the local loop, typically a twisted pair of copper wires. The present invention provides a method and apparatus to determine the optimal sampling instant of the received data stream. The present invention provides a probing signal that is well-suited for use in determining the channel's response to a known sequence of PCM codes used as data symbols. This is especially useful in so-called PCM modulation schemes that utilize the DTN, where knowledge of network and DAC distortion predicates the selection of available PCM codes used to represent data.

Abstract: An equalizer for filtering a received signal to generate a filtered signal.

Abstract: A method of controlling a line equalizer such as a modem includes an extracting step of extracting plural tone signals each superimposed on a transmission signal and having a specific frequency component; a judging step of judging levels of the extracted tone signals; and a controlling step of controlling characteristic of a line equalizer which equalizes a receive signal, based on the levels of the judged tone signals. A line equalizer is controlled without performing an exchange of a training signal prior to starting a data transmission and without increasing the amount of hardware of a modem or the like.

Abstract: A noise canceler according to the invention orthogonally transforms a noise frame by means of an FFT and sorts its transform coefficients into N groups by means of a group by group basic reduction value determining section. Then, it compares the mean value of the transform coefficients of each of the groups with a threshold value and determines a basic reduction value according to the outcome of the comparison. Then, it operates to suppress the transform coefficients produced from the FFT by means of a transform coefficient suppressing section on the basis of the basic reduction value.

Abstract: A direct-sequence CDMA receiver comprises power detectors for receiving a spread spectrum signal for detecting the power levels of user channels. A channel ranking circuit determines the ranks of the power levels. A framing circuit segments the received spread spectrum signal into data blocks and appending, to each of the data blocks, a header containing channel numbers identifying the user channels arranged according to the determined power level ranks. A plurality of serial interference cancellation stages are provided, each including interference cancelers arranged in descending order of ranks. Each interference canceller detects one of the channel numbers of the header corresponding to the rank of the interference canceler, and removes one or more interfering signals from an associated user channel by using a despreading code that corresponds to the detected channel number.

Abstract: A method for a wireless discrete tone communications system, synchronizes the remote station to the base station. The method begins with the step of generating a clock signal at the base station. The base station then derives a synchronization symbol pattern from the base station clock signal and spreads the it with spreading codes that distributes the symbol pattern over a plurality of discrete tones, forming a discrete tone signal. The base station then transmits the spread signal to the remote station. The remote station generates a first clock signal and samples the discrete tones using the remote station first clock signal, forming a first sampled signal. Then the remote station applies the first sampled signal to a matched filter bank, forming a frequency error signal. The method then adjusts a frequency of the remote station first clock signal using the frequency error signal, forming a second clock signal.

Abstract: A receiver time at the reception instant of a transmission time marker contained in received data elements is determined. A multiplicity of successively received data elements are stored, and a receiver time which corresponds to a data element reception instant is also stored. Then the stored data elements are searched for a transmission time marker, and the receiver time is determined which corresponds to the reception instant of the transmission time marker, using the stored receiver time(s). The novel method is distinguished by the fact that the receiver time which corresponds to the reception instant of a single data element is stored per specific or indefinite multiplicity of stored data elements, and that the determination of the receiver time corresponding to the reception instant of the transmission time marker takes place on the basis of the stored receiver time(s). The determination is effected by extrapolating or interpolating based on the stored receiver time(s).

Abstract: Method and device for generating bit information in a subscriber station of a bus system, in particular of the bus of the EIBA, essentially symmetrical AC voltage information being superposed as bit information on a DC voltage of the bus in that a DC voltage potential (19) of a line under inductive loading (9) is pulled, in each case in an active pulse (20) to the potential of another line and an equalizing pulse (22, 23) is formed with subsequent energy recovery. It is provided that the active pulse (20) of the bit information at a bit frequency is formed from individual pulses (17) of higher frequency.

Abstract: An apparatus for performance improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal, wherein each of the plurality of received signals is weighted and combined to provide the processed signal; and a generation circuit for computing a weight vector. The weight vector has a number of weights greater than the plurality of received signals and is computed as a least-squares problem solution.

Abstract: The present invention expands the range over which a wireless powered communication device (500) and device reader (12) can communicate. In the present invention, circuitry (502) within the device (500) provides for determining a characteristic of the received communication signal. Based upon this signal characteristic data recovery parameters are adapted to enhance data recovery over a maximize communication distance. In a preferred embodiment of the present invention, the magnitude of the power signal is observed. It is known that the power signal varies as an inverse square of the distance of the device (500) to the reader. From this information, a data detection threshold is adjusted to enhance data recovery.

Abstract: A digital receiver includes a mixer stage receiving a carrier signal S(t) and delivering an intermediate frequency signal S.sub.FI (t) to a demodulation stage. The mixer stage is furnished with a PLL circuit for generating a signal at a given frequency. The digital receiver further includes a phase noise digital correction stage for tapping off a noise signal .phi..sub.n (t) generated by the PLL circuit in the mixer stage and for compensating the noise signal .phi..sub.n (t) in the demodulation stage.

Abstract: A mobile station (104) in a DS-CDMA communication system (100) has receiver diversity. A first antenna (130) receives signals over a communications channel (101) from a base station (102). A second antenna (132) receives signals which are delayed in a delay element (142) by one or more chip times and combined in a summer (148) with signals from the first antenna. The combined signals are presented to a RAKE receiver (112) for decoding and demodulation. When discernible multipath energy is present to the point where much of the received signal energy is not accounted for in the assigned RAKE receiver fingers, the second antenna is switched out to avoid increasing the level of interference.

Abstract: A method for a wireless discrete multitone spread spectrum communications system, synchronizes the remote station to the base station. The method begins with the step of generating a clock signal at the base station. The base station then derives a synchronization symbol pattern from the base station clock signal and spreads the it with spreading codes that distributes the symbol pattern over a plurality of discrete tones, forming a discrete multitone spread spectrum signal. The base station then transmits the spread signal to the remote station. The remote station generates a first clock signal and samples the discrete tones using the remote station first clock signal, forming a first sampled signal. Then the remote station applies the first sampled signal to a matched filter bank, forming a frequency error signal. The method then adjusts a frequency of the remote station first clock signal using the frequency error signal, forming a second clock signal.

Abstract: A spread spectrum protocol in a power line communication (PLC) system uses Harmonic Modulation (HM) as true spread spectrum modulation made up of a plurality of modulated tones spaced in frequency with equal distance between adjacent tones. The protocol incorporates the following modes:"Conventional"--Master/Slave relation of meters to a common hub."Leap Frog"--performing data relay through locally elected/designated meters for relay to a central hub or a distributed set of concentrators."Alarm Channel"--reserving an HM signal set for meters to telemeter their configuration in a subnetwork after a power distribution network reconfiguration."Probing"--using HM polling to diagnose the location of a feeder fault."Derived Timing"--master derived timing for inbound message framing."Rate Adapting"--allocating a mix of number of HM channels to the outbound/inbound ratio according to message traffic control requirements and power line distribution topology.

Abstract: A metric sifting, i.e., sorting or selection, method which can efficiently provide a sorted set of survivor metrics during breadth-first reduced-search decoding of convolutional codes. The preferred embodiment efficiently implements the M algorithm by providing a sorted set of M survivor metrics using a linear-time (O(M)) number of comparisons. To obtain this efficiency, the method employs partitioning of branch metrics into implicitly sorted subsets, and employs efficient merging of these subsets. Compared to the prior art, the number of comparisons for metric sifting during M algorithm decoding of typical rate 1/n binary convolutional codes is reduced by 30-40%; more specifically, the number of comparisons is reduced from (2n-1)M-(n-1) to n(M-1)+2.sup.n -1.

Abstract: A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

Abstract: A method synchronizes a remote unit to a base station in a bandwidth efficient communication system and includes generating a clock signal at the base station. The clock signal is spread over a plurality of non-uniformly spaced discrete tones, thus creating a synchronization signal at the base station, which is transmitted from the base station and received at least one remote unit. Matched filtering is performed on the synchronization signal at the remote unit and the remote unit generates a remote clock signal synchronized with the synchronization signal, based on the matched filter output.