Abstract: A spread spectrum communication receiver includes a plurality of fingers each including a despreader part, an inverse-orthogonal conversion part and a demodulation part. A channel combining part combines demodulated symbols of the plurality of fingers. A control part controls the plurality of fingers on the basis of orthogonal channel allocation information and channel state information so that the fingers execute a RAKE process when the channel information indicates that data to be transmitted is allocated to one orthogonal channel at a transmitter and the fingers perform parallel demodulation processes then the channel information indicates that data to be transmitted is allocated to a plurality of orthogonal channels at the transmitter.

Abstract: A detector detects the end of a serial bit stream wherein the serial bit stream is based on one clock and the detector (and other associated circuitry) is based on a different, asynchronous clock. An Exclusive OR block receives the serial bit stream and a digital strobe signal according to IEEE High Performance Serial Bus Specification 1394. Based on this standard, one but not both of the serial bit stream and digital strobe signal changes level every data interval. The Exclusive OR block outputs a periodic signal when the serial bit stream and digital strobe signal are present but outputs a constant digital level upon termination of the serial bit stream and digital strobe signal. The detector also includes a first register coupled to receive the output of the receiver, a second register coupled to receive the output of the first register and a third register coupled to receive the output of the second register. All three registers are clocked simultaneously.

Abstract: A data-link processing equipment which reduces the processing delay of the data-link data and performs the data-link processing with a good efficiency and an apparatus for a subscriber terminal office using this equipment. This data-link processing equipment provides a data-link synchronizing unit which establishes the synchronization of the data-link data extracted from frame synchronizing units respectively for a plurality of digital transmission lines; a data-link interface unit which latches the data-link data and outputs a data update flag; and a processor which reads and processes the latched data-link data by using the data update flag as an interrupt signal.

Abstract: A system for communicating digital information over wires having a great deal of harmonic distortion, such as a power line, employs a transmitter which transmitter which creates a carrier wave for each of a plurality of signals to be sent. This carrier wave has frequency lobes positioned between the frequency lobes of the harmonic distortion. Each of the lobes of a single carrier signal is encoded with the same bit value during a given bit period. This signal is then mixed with any existing signal on the wire. At a remote receiver coupled to the wires, the signal is sensed, filtered, and Fourier transformed into coefficients. The signal-to-noise (S/N) ratio of each Fourier coefficient is determined by a novel S/N estimation technique. The coefficients are weighted based upon the S/N ratio estimation, and decoded, preferably by an inner product of the weighted Fourier coefficients. Additionally, the S/N ratio estimates could be time averaged before being used in the weighting and bit decoding.

Abstract: A post-cursor tap coefficient of a decision feedback equalizer is used as a coefficient of an echo canceler during a cold-start echo canceler training period in which a communication start-up training is carried out in an initial state and during a cold-start received signal detection period, so that an echo cancellation characteristic can be improved without increasing the circuit scale of the echo canceler and a high-speed, error-free received signal detection can be attained.