Abstract: A 3D memory device may include a logic device layer on a substrate and a memory device layer stacked on the logic device layer. The logic device layer may include logic devices disposed on the substrate. The memory device layer may include a word line stack disposed in an extension area, staircase patterns disposed in the word line stack, a dielectric layer stack in a peripheral area, and capacitors inlayed in the dielectric layer stack.

Abstract: A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

Abstract: A semiconductor device of an embodiment includes first and second structures arranged in a first hierarchy, in which the first and second structures are repeatedly arranged in a first direction along a plane of the first hierarchy, and a distance between geometric centers of the first and second structures in a minimum unit of repetition of the first and second structures differs between a first position and a second position in the first direction.

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

Abstract: A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

Abstract: A non-volatile memory cell includes a thin film resistor (TFR) in series and between a top state influencing electrode and a top wire. The TFR limits or generally reduces the electrical current at the top state influencing electrode from the top wire. As such, non-volatile memory cell endurance may be improved and adverse impacts to component(s) that neighbor the non-volatile memory cell may be limited. The TFR is additionally utilized as an etch stop when forming a top wire trench associated with the fabrication of the top wire. In some non-volatile memory cells where cell symmetry is desired, an additional TFR may be formed between a bottom wire and a bottom state influencing electrode.

Abstract: The present disclosure provides an antifuse array structure and a memory. The antifuse array structure includes a plurality of antifuse integrated structures arranged in a bit line extension direction and a word line extension direction to form an antifuse matrix. The antifuse integrated structure is arranged in a same active region, and an extension direction of the active region is the same as the bit line extension direction. Each antifuse integrated structure includes a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor. The first switch transistor and the second switch transistor are respectively controlled through two adjacent word lines, the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are respectively controlled through two adjacent programming wires, and the programming wire is further configured to control adjacent antifuse integrated structures.

Abstract: A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.

Abstract: The present application provides an anti-fuse one-time programmable (OTP) memory array and a manufacturing method of the anti-fuse one-time programmable (OTP) memory array. The memory array includes: active areas; pairs of programming word lines and read word lines; and dummy word lines. The active areas extend along a first direction in a semiconductor substrate, and are separately arranged along a second direction. The programming word lines, the read word lines and the dummy word lines extend along the second direction over the semiconductor substrate. A region in which a pair of programming word line and read word line are intersected with one of the active areas defines a unit cell in the memory array. The dummy word lines respectively lie between adjacent pairs of programming word lines and read word lines. A region in which one of the dummy word lines is intersected with one of the active areas defines an isolation transistor.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

Abstract: A semiconductor storage device includes a substrate with a memory cell region and a first region to one side of the memory cell region. A first memory cell layer is on the substrate. A second memory cell layer is between the first memory cell layer and the substrate. A plurality of first conductive layers are stacked on each other in the first memory cell layer. A plurality of second conductive layers are stacked on each other in the second memory cell layer. A plurality of first contacts are above the first region of the substrate, extending through second conductive layer from the substrate to the first memory cell layer. The contacts are electrically insulated from the second conductive layers and electrically connected to ends of the first conductive layers in the first region.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.

Abstract: A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.