Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: A power supply including a bi-directional DC converter and a control method thereof are disclosed herein. The power supply includes first to third terminals, first and second semiconductor switches and a mode switching circuit. The first terminal is electrically coupled to an external power source. The second terminal is electrically coupled to a load. The third terminal is electrically coupled to a battery. The first and second semiconductor switches are electrically coupled in series between the first and second terminals. The mode switching circuit is electrically coupled to the first semiconductor switch, the second semiconductor switch and a bi-directional DC converter, respectively. The bi-directional DC converter is further electrically coupled to an intermediate node between the first semiconductor switch and the second semiconductor switch, and to the third terminal.

Abstract: A digitally controlled oscillator, including: a frequency divider chain, configured to perform frequency division on an input clock signal to produce K basic clock signals, wherein frequencies and periods of the K basic dock signals are the same and a time difference between two adjacent basic clock signals is a basic time unit; and a frequency synthesizer, configured to receive the K basic clock signals from the frequency divider chain, determine a first period and a second period according to the basic time unit and a frequency control word, and generate a synthetic clock signal based on the K basic clock signals, wherein the synthetic clock signal uses the first period and the second period in an alternate manner.

Abstract: A power control circuit comprising a power supply and a load, the load being synthesized from an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped in impedance modules. The impedance elements in each impedance module are of equal value, while those between the modules bear ratios uniquely defined according to the numbers of impedance elements in the impedance modules. A number of switches associated with said impedance elements short out a selected number of the impedance elements under the control of a first analog signal which may be preprocessed by an analytic function. The analog signal is converted to digital signals by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, whereby the amount of power delivered to the load is controllable by the first analog signal.

Abstract: Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an output, a third transistor coupled to a second input, a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output, a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current, and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on (with adjustable VOUT ramp rate) the fourth transistor with a constant ramp rate.

Abstract: A circuit includes a first transistor including first and second current terminals. The first current terminal couples to a supply voltage node. A second transistor includes a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at an output node and the fourth current terminal couples to a ground node. A third transistor includes a third control input and fifth and sixth current terminals. The fifth current terminal couples to the output node and the sixth current terminal couples to the ground node. A fourth transistor includes a fourth control input and seventh and eighth current terminals. The eighth current terminal couples to the ground node and the seventh current terminal couples to the third control input. An inverter having an input coupled to the second control input and an output coupled to the fourth control input.

Abstract: A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

Abstract: Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.

Abstract: A control device may be configured to control an amount of power delivered to one or more electrical loads and provide various feedback associated with the control device and/or the electrical loads. The control device may be a wall-mounted device or a battery-powered remote control device. The feedback may indicate the amount of power delivered to the one or more electrical loads. The feedback may also indicate a low battery condition. The control device may include a light bar and/or one or more indicator lights for providing the feedback.

Abstract: According to an embodiment, a power source circuit has first, second, and third one-conductivity-type transistors with commonly connected emitters, wherein the first transistor has an emitter area that is N times those of the second and third transistors. The power source circuit outputs a reference voltage that is set by a voltage drop that is caused at a resistance between bases of the first and second transistors and a forward voltage of a PN-junction diode, and outputs a BG_OK signal in response to a potential at a collector of the third transistor.

Abstract: The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF?) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.

Abstract: Various examples are provided related to switched-capacitor converters (SCCs) with multi resonant frequencies. In one example, a multi resonant SCC (MRSCC) includes a series of switches coupled between an input voltage and an output connection; a pair of diodes coupled across the output connection; and a resonant circuit coupled at a first end between first and second switches of the series of switches and at a second end between the pair of diodes. The resonant circuit can comprise a resonant tank including a first capacitor and a resonant inductor, and a resonant component in parallel with at least a portion of the resonant tank. The resonant component can be connected across the resonant tank or across the resonant inductor. The MRSCC topology can also be used with higher voltage conversion ratio converters.

Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.

Abstract: A phase-locked loop (PLL) has a first divider that receives a first reference clock signal and supplies a first divided reference clock signal. A second divider receives a second reference clock signal and supplies a second divided reference clock signal. On switching between use of reference clock signals, when the phase difference between the first divided signal and the second divided signal includes one or more clock periods of the second reference clock signal, the PLL performs a phase adjust to remove the one or more clock periods. The phase adjust can be performed in the feedback divider or as an offset in the loop if digital edges of the clock signals are available. The phase adjust ensures the phase adjust on the PLL output caused by switching reference clocks is the phase difference between the reference clock signals before division.

Abstract: One example discloses a voltage select circuit, comprising: a first input configured to receive a first input voltage; a second input configured to receive a second input voltage; a first diode having a first polarity coupled to the first input; a second diode having a first polarity coupled to the second input; an output coupled to a second polarity of both the first and second diodes; a diode bypass circuit coupled to the first input and the output in parallel with the first diode, and coupled to the second input; and wherein the bypass circuit is configured to pass the first input voltage to the output if an absolute value of the second input voltage is less than a voltage drop of the second diode.

Abstract: Embodiments of the disclosed technology comprise methods and/or devices for performing measurements and/or manipulations of the collective state of a set of Majorana quasiparticles/Majorana zero modes (MZMs). Example methods/devices utilize the shift of the combined energy levels due to coupling multiple quantum systems (e.g., in a Stark-effect-like fashion). The example methods can be used for performing measurements of the collective topological charge or fermion parity of a group of MZMs (e.g., a pair of MZMs or a group of 4 MZMs). The example devices can be utilized in any system supporting MZMs.

Abstract: To control a drive voltage of a transistor to be constant in a circuit that captures signals. A duty ratio control unit changes a duty ratio of a predetermined input periodic signal and outputs the predetermined input periodic signal as an output periodic signal. A transistor is a transistor that outputs an input signal input to a source from a drain as an output signal. A charge control unit charges the condenser with a predetermined voltage in a case in which the output periodic signal is not at a specific level. A transistor drive unit applies the charged predetermined voltage between a gate and the source of the transistor in a case in which the output periodic signal is at the specific level.

Abstract: Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

Abstract: An apparatus for phase and frequency detection (PFD) includes a first circuit to receive a first input pulse and to generate a first output pulse, the rising edge of which is triggered by a first rising edge of the first input pulse, and a second circuit coupled to the first circuit and configured to receive a second input pulse and to generate a second output pulse, the rising edge of which is triggered by a second rising edge of the second input pulse. The second output pulse has a falling edge carrying first information related to a first rising edge of the first input pulse. The first output pulse has a falling edge carrying second information related to a second rising edge of the second input pulse.

Abstract: An apparatus is disclosed that implements frequency synthesis with accelerated locking. In an example aspect, the apparatus includes an oscillating signal source, a modulus compensator, and a frequency generator. The oscillating signal source is configured to provide a reference signal having a reference frequency. The modulus compensator is coupled to the oscillating signal source and is configured to receive the reference signal. The modulus compensator is configured to produce a compensated modulus value based on the reference frequency, a fixed oscillator frequency of a fixed-frequency oscillator signal, and a modulus value. The frequency generator is coupled to the oscillating signal source and the modulus compensator and is configured to receive the compensated modulus value. The frequency generator is configured to generate an output signal having an output frequency that is based on the reference frequency and the compensated modulus value.