Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

Abstract: A multi-terminal DC electrical network comprises a plurality of DC terminals, each DC terminal operatively connected to at least one other DC terminal via a respective DC power transmission medium; a plurality of converters, each converter being operatively connected to a respective one of the DC terminals, the plurality of converters including at least one designated converter; and a controller including a solver configured to use an algorithm to process a plurality of values to compute a no-load DC voltage for a first designated converter as a function of the plurality of values. The plurality of values include a first value defining an operating mode of each designated converter; a second value defining a default electrical characteristic of the multi-terminal DC electrical network or a computation parameter of the algorithm; and a third value defining an electrical measurement corresponding to a voltage or current in the multi-terminal DC electrical network.

Abstract: A signal calculator includes a capacitor and a variable current source. The variable current source charges the capacitor and generates a current corresponding to a predetermined voltage during a first period. A first voltage is generated using a voltage of the capacitor charged during an enable period of a first signal in the first period, and a second voltage is generated using a voltage of the capacitor charged during the first period. The variable current source further generates a current corresponding to the second voltage during a second period. A second signal is generated according to a result of comparing the first voltage with the voltage of the capacitor during the second period, and a fourth voltage is generated by generating and sampling a third voltage which is increased according to a first current during an enable period of the second signal in the second period.

Abstract: A switch matrix, a switch matrix assembly, and a magnetic resonance imaging (MRI) apparatus are disclosed. The switch matrix includes a first path to which an electric signal is applied; a first switching unit configured to selectively and electrically interconnect a first input unit and a first end of the first path or to open the first end of the first path; and a second switching unit configured to selectively and electrically connect a second input unit to a second end of the first path or to open the second end of the first path.

Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.

Abstract: A level shift includes a bias voltage providing circuit, a level shifting circuit and an output switching circuit. The level shifting circuit includes a high level shifting unit and a low level shifting unit. When the high level shifting unit is in a cut-off state, the high level shifting unit further receives a first bias voltage such that the high level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the high level shifting unit. When the low level shifting unit is in a cut-off state, the low level shifting unit further receives a second bias voltage such that the low level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the low level shifting unit. The level shifter of the present application provides a higher response speed.

Abstract: Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.

Abstract: A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing a voltage regulator. The voltage regulator includes a power field effect transistor (FET) comprising a gate terminal. The voltage regulator further includes a charge pump, the charge pump comprising a capacitor switchably coupled to the gate terminal. The voltage regulator further includes a current outputting amplifier switchably coupled to the capacitor.

Abstract: Provided is a heat radiation unit for radiating heat generated during operation of a wireless power transmitting or receiving device and includes a plurality of thermally conductive metal layers stacked in two or more layers and an adhesive layer for attaching the thermally conductive metal layers, to prevent lowering of the charging efficiency and improve the heat radiation performance.

Abstract: The present disclosure relates to a power transmitter, a resonance-type contactless power supply and a control method. The inverter circuit is controlled to provide a high-frequency AC current with a voltage strength parameter so that a current strength parameter (e.g. a peak value or an effective value of the current) of the AC current flowing through a transmitting coil and that through a receiving coil have a predetermined relationship. Thus, an equivalent load impedance is adjusted so that the system efficiency is optimized.

Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.

Abstract: Certain aspects involve a powered shelf system that can inductively provide power to electrical components of consumer product packages. The powered shelf system can include a housing, a primary inductor, a controller, and a pusher system. The primary inductor can be coupled to or included in the housing. The controller can apply an electrical current to the primary inductor in accordance with a maximum power requirement for the powered shelf system. The applied electrical current can be sufficient to create a magnetic field from the primary inductor that has a minimum field strength at a specified distance from the primary inductor. The minimum field strength can be sufficient to induce a minimum current in a secondary inductor for powering an emitting device that is electrically coupled to the secondary inductor. The pusher system can position the secondary inductor at the distance from the primary inductor.

Abstract: A switchable charge pump (SCP) combines a switching element and a charge pump. An SCP can be utilized within an RF circuit to allow the charge pump to be activated or deactivated in the circuit depending on incident RF power level. Multiple SCPs can be utilized to provide a generalized a single-pole N-throw (SPNT) system architecture. In one example, an RF transmit-receive (T/R) system utilizes SCPs to operate in one of three modes: transmit mode, receive mode, or self-selecting terminate mode.

Abstract: Structures and techniques, using superconducting Josephson-junction based circuits, to directly engineer physical multiqubit (or “many-qubit”) interactions in a non-perturbative manner. In one embodiment, a system for multiqubit interaction includes: a multispin coupler including a plurality of loops, each loop having a pair of Josephson junctions; and a plurality of qubits each inductively coupled to the multispin coupler.

Abstract: A power control apparatus comprises a conversion unit which is capable of collectively converting DC power output by each of the plurality of power supply apparatuses to AC; and a communication unit which communicates with an external equipment control apparatus in accordance with a predetermined communication protocol. The communication unit notifies the equipment control apparatus of an equipment class of the power control apparatus in addition to notifying the equipment control apparatus of an equipment class of each of the plurality of power supply apparatuses.

Abstract: A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise.

Abstract: In one embodiment, a multiple interleaved coil structure for wireless power transfer includes a plurality of incomplete coils, each of the plurality of incomplete coils configured such that an alternating current flowing in the incomplete coil produces a magnetic field, and at least one interconnect between the plurality of incomplete coils, the at least one interconnect including a plurality of conductors arranged in such a way that the alternating current flowing in the plurality of conductors does not produce a magnetic field. Each of the plurality of incomplete coils includes a plurality of non-contiguous segments arranged in such a way that the incomplete coil will emit magnetic flux in response to an applied alternating current. The multiple interleaved coil structure can be implemented in a wireless power transmitter or a wireless power receiver.

Abstract: A transmitter including a transmitter board comprising multiple electrical ports, each port configured to: receive any of a plurality of antenna boards, and provide electrical signals to a received antenna board. Each respective antenna board comprises antenna elements configured to transmit radio frequency (RF) power waves using the provided signal. The transmitter board further includes a processor configured to: determine whether antenna boards are connected to respective ports of the multiple electrical ports, and after determining that a respective antenna board has been received at a respective port: (i) instruct the transmitter board to provide, via the respective electrical port, electrical signals to the antenna board, and (ii) control transmission of RF waves by antenna elements of the respective antenna board to cause each of the RF waves to constructively interfere with at least one other RF wave at a receiver device located within a transmission field of the transmitter.

Abstract: A domestic appliance heating apparatus includes a heating element having two heating connections connected to two supply connections of a supply network, respectively. A first switching element is connected between one of the two heating connections and one of the two supply connections and a second switching element is connected between the other one of the two heating connections and the other one of the two supply connections. A measuring unit has at least one measuring input, at which a potential is present in at least one heating operating state. A control unit interrupts in a network form recognition operating state a conduction path through the heating element by means of the first switching element while the second switching element is closed and takes into account a first potential present at the measuring input when determining a network form present at the heating element.