Abstract: A method and apparatus for measuring a voltage of a battery pack are provided. A battery control apparatus may include a voltage distributor configured to distribute a voltage of a battery pack including battery modules, using distribution elements connected to the battery pack, and a voltage extractor configured to extract a voltage value of the voltage of the battery pack by measuring the distributed voltage.

Abstract: A method including operations of receiving an input clock at an input node, coupling the input node to a first internal node using a first capacitor, inverting a first internal signal at the first internal node into a first interim signal at a first interim node using a first inverter, coupling the first interim node to the first internal node using a first resistor, coupling the input node to a second internal node using a second resistor, inverting a second internal signal at the second internal node into a second interim signal at a second interim node using a second inverter, coupling the second interim node to the second internal node using a second capacitor, and using a buffer to receive the first interim signal and the second interim signal and output a first phase and a second phase of an output clock.

Abstract: In one semiconductor chip, driving transistors, a current sensor, and a temperature sensor for sensing a temperature of a driver area are arranged in a driver area, and a current sensing circuit, an analog-digital converter, and a temperature sensor for sensing a peripheral circuit area are arranged in a peripheral circuit area. A correction circuit unit corrects a digital sensed voltage from the analog-digital converter based on a sensing result of the temperature sensor of the driver area and a sensed result of the temperature sensor of the peripheral circuit area.

Abstract: A self-gating flip-flop circuit includes a flip-flop circuit and a clock circuit. The flip-flop circuit includes a clock input. The clock circuit is coupled to the clock input. The clock circuit includes a latch circuit, a reset circuit, and a gate circuit. The reset circuit is coupled to the latch circuit. The gate circuit is coupled to the latch circuit and the clock input.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: Circuits, devices, and methods for operating a charge pump. In some implementations, a charge pump module includes a clock circuit configured generate to a first clock signal and a second clock signal, the first clock signal having a lower frequency than the second clock signal. The charge pump module also includes a driving circuit configured to generate a first set of clock signals based on the first clock signal and a second set of clock signals based on the second clock signal, the driving circuit coupled to the clock circuit. The charge pump module further includes a charge pump core including a set of capacitances, the charge pump core configured to charge the set of capacitances based the first set of clock signals and the second set of clock signals.

Abstract: Arrangement for controlling a voltage signal between gate and emitter terminals (G-E) of a switch type power semiconductor component, such as an IGBT transistor, such that the voltage signal is formed at least partly by means of a resistance and a switch (RGON1-SGON1, RGOFF1-SGOFF1) connected in series between an auxiliary voltage (+UG4, ?UG4) of a gate controller and the gate terminal (G) of the IGBT. The arrangement is adapted to control the switch (SGON1, SGOFF1) with a high frequency of at least 1 MHz and with a duty cycle adjusted such that the measured rate of change of a collector voltage of the IGBT being controlled is set in accordance with a reference value received from a control unit of the device.

Abstract: Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an output, a third transistor coupled to a second input, a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output, a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current, and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on (with adjustable VOUT ramp rate) the fourth transistor with a constant ramp rate.

Abstract: A reference voltage circuit with current buffer including a low voltage reference to output a low voltage, a first resistor-capacitor (RC) filter to filter the low voltage, a buffer circuit to output a current to be used by a load, a second RC filter associated with the load, and a capacitor in parallel with the buffer circuit configured to increase a rise time of the buffer.

Abstract: A circuit for controlling a high-side power switch includes a level shifting circuit configured to receive an input signal for selectively configuring a logic command circuit to be in a set state, for providing a first output signal to the high-side power switch, and in a reset state, for providing a second output signal, different from the first output signal, to the high-side power switch. The circuit also includes a regulation circuit configured to detect an indicative signal indicative of the output signal provided to the high-side power switch and to change sensitivity of the level shifting circuit to the input signal, based on the indicative signal that is detected.

Abstract: An electrical apparatus is connected to a power supply and changes operation in accordance with variation of a power supply voltage of the power supply in accordance with drive of another electrical apparatus connected to the same power supply. The electrical apparatus includes a drive unit driven by the power supply, a voltage detection unit, a current detection unit, and a control unit which sets a threshold value with which a circuit breaker which breaks the power supply is not driven, based on (i) a power supply voltage of the power supply detected by the voltage detection unit when the drive unit is driven, (ii) a power supply voltage of the power supply detected by the voltage detection unit when the drive unit is not driven, and (iii) a current detected by the current detection unit when the drive unit is driven.

Abstract: An apparatus for receiving wireless power is provided. The apparatus a communication circuit configured to transmit a first indication of a first wireless charging category associated with the apparatus. The communication circuit is further configured to receive an indication of a wireless charging class of a power transmit unit (PTU). The communication circuit is further configured to transmit a second indication of a second wireless charging category associated with the apparatus based on the wireless charging class of the PTU being compatible with a higher wireless charging category than the first wireless charging category. The apparatus further comprises a coupler configured to receive a level of wireless power corresponding to the second wireless charging category. The higher wireless charging category indicates an ability to receive a greater amount of wireless power than the first wireless charging category.

Abstract: A device includes a plurality of high voltage cells (HVC) coupled to a plurality of resistors, and a controller. The plurality of HVC generates an output voltage that is higher than an input voltage to the plurality of HVC. The controller receives a reference voltage and an output voltage from a resistor of the plurality of resistors. The controller generates a signal responsive to a difference between the reference voltage and the output voltage. The controller forms a closed feedback loop with the plurality of HVC and the plurality of resistors. The generated signal is input to the plurality of HVC. A substrate of a resistor of the plurality of resistors is biased to an output of at least one high voltage cell of the plurality of HVC. Output of the at least one high voltage cell is input to another high voltage cell.

Abstract: An electrical circuit includes a monolithic integrated circuit (IC) switch device that includes a first pin, a second pin, and a power switch that connects the first pin to the second pin through the power switch when the electrical circuit is turned ON. The monolithic IC switch device includes an adaptive safe operating area (SOA) circuit that limits allowable current through the power switch based on temperature, such as the temperature of the power switch.

Abstract: Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

Abstract: According to some aspects, a quantum circuit is provided including a plurality of non-linear circuit elements coupled together in series and in parallel, such that at least two of the circuit elements are coupled together in series and at least two of the circuit elements are coupled together in parallel, wherein the quantum circuit is configured to act as an amplifier.

Abstract: Structures and techniques, using superconducting Josephson-junction based circuits, to directly engineer physical multiqubit (or “many-qubit”) interactions in a non-perturbative manner. In one embodiment, a system for multiqubit interaction includes: a multispin coupler including a plurality of loops, each loop having a pair of Josephson junctions; and a plurality of qubits each inductively coupled to the multispin coupler.

Abstract: Designing phase shifters having small insertion loss and footprint for mm-wave applications is challenging. The disclosed methods and devices provide solutions to overcome such challenge. Devices based on limited ground coplanar waveguide structure are also disclosed wherein the 180° phase shift is created using through and changeover mm-wave switches.

Abstract: A photovoltaic system includes groups of solar cells that can be switched in and out of the photovoltaic system. In response to detecting initiation of rapid shutdown, a control circuit controls a switch device to switch out a group of solar cells to lower the output voltage of the photovoltaic system below a safety level. In response to detecting a release trigger that indicates resumption of normal operation, the control circuit controls the switch device to switch back the group of solar cells to restore the output voltage of the photovoltaic system to a normal operating level. Solar cells may be switched out by disconnecting them from the photovoltaic system and switched back by reconnecting them into the photovoltaic system. Solar cells may also be switched out by shorting them out of the photovoltaic system and switched back in by removing the short.

Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.