Abstract: A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium semiconductor nanowires that are substantially defect free. The lateral epitaxial growth process is unidirectional due to the use of masks to prevent epitaxial growth in both directions, which would create defects when the growth fronts merge. Stacked sacrificial material nanowires are first formed, then after masking and etching process to reveal a semiconductor seed layer, the sacrificial material nanowires are removed, and III-V compound semiconductor or germanium epitaxy is performed to fill the void previously occupied by the sacrificial material nanowires.

Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.

Abstract: Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One embodiment of an SST die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. The reflective material has a higher reflectivity than a base material of the connectors such that light traveling toward the connectors reflects back out of the device.

Abstract: A display substrate includes a first switching element electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction, an organic layer disposed on the first switching element, a shielding electrode disposed on the organic layer and overlapping the data line, a pixel electrode disposed on the same layer as the shielding electrode and a light-blocking pattern disposed on the shielding electrode and adjacent to a corner of the pixel electrode.

Abstract: A method for producing a thin-film photovoltaic device (1), comprising the following steps: providing a substrate (2); placing a photovoltaic film (3) on said substrate by stacking layers comprising at least a first conductive layer (4) forming a rear electrical contact, a second photoactive layer (5) that is absorbent in the solar spectrum and is made from an inorganic material, and a third layer (6) made from a transparent conductive material forming a front electrical contact; —dividing the photovoltaic film into a plurality of individual and interconnected photovoltaic cells (30), —forming a plurality of individual holes (31) passing at least through the first and second layers of photovoltaic film in each cell, by applying a mask (8) according to a printing method, in particular material-jet digital printing, flexography, screen printing, or pad printing, said mask having main areas defining a positive or negative stencil for said holes. The present invention is applicable in the field of solar glazing.

Abstract: Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes include a photon-reflective material.

Abstract: A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring.

Abstract: One embodiment of the invention can provide a system for fabricating a photovoltaic structure. During fabrication, the system can form a sacrificial layer on a first side of a Si substrate; load the Si substrate into a chemical vapor deposition tool, with the sacrificial layer in contact with a wafer carrier; and form a first doped Si layer on a second side of the Si substrate. The system subsequently can remove the sacrificial layer; load the Si substrate into a chemical vapor deposition tool, with the first doped Si layer facing a wafer carrier; and form a second doped Si layer on the first side of the Si substrate.

Abstract: Integrated circuits for a single-molecule nucleic-acid assay platform, and methods for making such circuits are disclosed. In one example, a method includes transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) substrate, and forming a pair of post-processed electrodes on the substrate proximate opposing ends of the one or more carbon nanotubes.

Abstract: A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.

Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side, and a side surface side of an air gap, while leaving part of the air gap between the silicon film formed on the upper surface side and the silicon film formed on the lower surface side. The method includes forming a metal film on a side surface of the slit. The method includes forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film. The method includes removing unreacted part of the metal film formed on the side surface of the slit.

Abstract: A novel emissive display assembly incorporates a photo-switchable polarizer that is switchable between an active, polarizing, state and an inactive, non-polarizing, state depending on the predetermined level of intensity of UV light in the ambient light and enhance the viewable quality of the emissive display by minimizing or eliminating UV light reflection on the emissive display.

Abstract: Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.

Abstract: An ion implanter may include an electrostatic clamp to hold a substrate; a plasma flood gun generating a flux of electrons impinging upon the substrate; and a controller coupled to the plasma flood gun and including a component generating a control signal responsive to a measurement signal, the control signal to adjust operation of the plasma flood gun to a target operating level. At the target operating level the flux of electrons may comprise a stabilizing dose of electrons, the stabilizing concentration of electrons, the stabilizing concentration reducing a clamp current variation in the electrostatic clamp to a target value, the target value being less than a second value of clamp current variation when the plasma flood gun is not operating.

Abstract: To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an impurity introduction method. To manufacture a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption using the transistor. A gate electrode including a tungsten oxide film whose composition is controlled is used. The composition or the like is adjusted by a film formation method of the tungsten oxide film, whereby the work function can be controlled. By using the tungsten oxide film whose work function is controlled as part of the gate electrode, the threshold of the transistor can be controlled. Using the transistor whose threshold voltage is controlled, a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption can be manufactured.

Abstract: The method includes the steps of: a) providing a silicon substrate including a first portion covered by the mask made from a carbonaceous material and a second doped portion, the mask including, at the surface, a surface layer including implanted ionic species and an underlying layer free of implanted ionic species, b) exposing the surface layer and the second portion to a SiCl4 and Cl2 plasma so as to deposit a silicon chloride SiClx layer on the second portion and etch the surface layer, c) etching the underlying layer so as to expose the first portion, and d) etching the silicon chloride SiClx layer so as to expose the second portion.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.

Abstract: The present invention provides a slim-bezel flexible display device and a manufacturing method thereof. A through hole is formed in a first base plate of a lower substrate in an area adjacent to an edge thereof. A conductive connection body is mounted in the through hole. The conductive connection body is connected to a circuit layout layer and a flexible connection circuit that is connected to a drive circuit board so as to have the drive circuit board and the circuit layout layer connected. Compared to the prior art, the present invention provides an arrangement that makes it not necessary for the side of the lower substrate associated with the circuit layout layer to provide an additional connection zone for connection with the flexible connection circuit so that an effective display zone of a flexible display device can be enlarged and a bezel area can be reduced.