Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.

Abstract: A method for manufacturing a semiconductor device includes: forming a first major electrode on a first major surface of a semiconductor substrate; forming a second major electrode on a second major surface of the semiconductor substrate opposite to the first major surface; carrying out a surface activating treatment to activate surfaces of the first and second major electrodes; carrying out a surface cleaning treatment to clean up the surfaces of the first and second major electrodes; and after the surface activating treatment and the surface cleaning treatment, simultaneously forming first and second Ni films on the first and second major electrodes respectively by a wet film forming method, wherein a ratio of crystalline Ni contained in the first and second Ni films is 2% or more.

Abstract: Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

Abstract: A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: A thin film transistor (TFT) array substrate is disclosed. In one aspect, the substrate includes a buffer layer formed over a substrate, a storage capacitor formed in the buffer layer and including a first electrode and a second electrode surrounding and insulated from the first electrode and a driving TFT formed over the buffer layer.

Abstract: According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.

Abstract: [Problem] To provide a dicing sheet that is with a protective film formation layer, can easily produce a semiconductor chip having a protective film having high uniformity and superior printing precision, is such that the peeling of the protective film and the dicing sheet can be easily performed, and has superior affixing ability of chips during dicing. [Solution] The dicing sheet with a protective film formation layer is characterized by a protective film formation layer being peelably provided on the adhesive layer of an adhesive sheet resulting from the adhesive layer, which contains an adhesive component and a free epoxy group-containing compound, being laminated onto a substrate film.

Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide.

Abstract: A substrate and a display device are provided. The substrate includes a plurality of pixel groups arranged in rows and columns, the pixel groups each include a 3×3 array of sub-pixels which are at least two red sub-pixels (R), at least two green sub-pixels (G), at least two blue sub-pixels (B) and one white sub-pixel (W) with the white sub-pixel (W) in the center of the 3×3 sub-pixel array. Sub-pixels of the pixel group constitute two pixel units, which share the white sub-pixel (W). Each pixel unit includes at least one red sub-pixel (R), at least one green sub-pixel (G), at least one blue sub-pixel (B) and one white sub-pixel (W). With this substrate, data volume and the number of outputting lines of a data chip can be reduced so as to simplify the structure of an array substrate or a color filter substrate.

Abstract: A semiconductor device includes a substrate structure. The substrate structure includes a protruding engagement member having an inner periphery defining a groove and an outer periphery, an oxide layer on the protruding engagement member, and a bonding material layer on the oxide layer. The semiconductor device also includes a micro-electromechanical system (MEMS) substrate having a bonging pad. The bonding pad of the MEMS substrate is bonded to the bonding material layer of the substrate structure.

Abstract: Methods of selectively removing silicon oxide are described. Exposed portions of silicon oxide and spacer material may both be present on a patterned substrate. The silicon oxide may be a native oxide formed on silicon by exposure to atmosphere. The exposed portion of spacer material may have been etched back using reactive ion etching (RIE). A portion of the exposed spacer material may have residual damage from the reactive ion etching. A self-assembled monolayer (SAM) is selectively deposited over the damaged portion of spacer material but not on the exposed silicon oxide or undamaged portions of spacer material. A subsequent gas-phase etch may then be used to selectively remove silicon oxide but not the damaged portion of the spacer material because the SAM has been found to not only preferentially adsorb on the damaged spacer but also to halt the etch rate.

Abstract: A pixel element structure is disclosed. The pixel element structure includes first, second, and third sub-pixel elements, each including a light-emitting region. At least one of the first, second, and third sub-pixel elements includes a light-transmitting region, where the light-emitting region includes an organic light-emitting diode light-emitting structure, and where the organic light-emitting diode light-emitting structure includes a first substrate, and a nontransparent anode, a pixel defining layer, an organic layer and a cathode, sequentially arranged above the first substrate.

Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.

Abstract: A manufacturing method of an AMOLED backplane includes manufacturing a TFT substrate and forming a corrugation structure on the TFT substrate, which includes raised sections and recessed sections alternating each other; coating organic photoresist on the TFT substrate that includes the corrugation structure formed thereon to form a planarization layer in such a way that an upper surface of a portion of the planarization layer corresponding to and located above the corrugation structure includes a curved configuration corresponding to the corrugation structure; forming a pixel electrode on the planarization layer in such a way that the pixel electrode shows a curved configuration; and forming, in sequence, a pixel definition layer that has an opening to expose the curved configuration and a photo spacer on the pixel electrode and the planarization layer.

Abstract: A device including a porous metal organic framework (MOF) disposed between two terminals, the device including a first state wherein the MOF is infiltrated by a guest species to form an electrical path between the terminals and a second state wherein the electrical conductivity of the MOF is less than the electrical conductivity in the first state. A method including switching a porous metal organic framework (MOF) between two terminals from a first state wherein a metal site in the MOF is infiltrated by a guest species that is capable of charge transfer to a second state wherein the MOF is less electrically conductive than in the first state.

Abstract: Discussed is a display device, that may include a substrate divided into a display area and a non-display area except the display area, a first light shielding film formed in the display area, a second light shielding film formed in the non-display area, and oxide thin film transistors and organic light emitting diodes, which are formed on the first light shielding film, wherein the first light shielding film and the second light shielding film are spaced apart from each other.

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor.

Abstract: One embodiment of the disclosure relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.