Abstract: Functions MINBUFLSN and LOWTRANLSN, implemented in a computerized routine, are defined and comprise first and second components of a checkpoint. MINBUFLSN is functionally related to a first update to a first of "dirty" data pages in the RAM buffer. LOWTRANLSN is functionally related to the earliest update of a sequence in a transaction table wherein each update corresponds to an uncommitted transaction. The two components are derived during write-ahead logging and stored in the log header periodically as a function of logging activity. Upon recovery, the checkpoint is retrieved and a functional comparison between the components thereof employed in the recovery algorithm. The conventional analysis pass of the recovery log is avoided and a reduced overhead during logging is provided as well as an efficient recovery.

Abstract: An information management system for writable optical discs, includes a disc (7) on which data (7a) and management information (7b) are recorded; an operating system (1) in which data in a read only optical disc can be managed by means of files, the operating system (1) having a read instruction (2) and a write instruction (3); read control portion (5) for changing the read instruction directed to the read only optical disc into a read address instruction directed to the disc (7), the read control portion (5) having modifying and loading portion (5b) for changing the management information (7b) into mutual information having a format of the read only optical disc; internal storage (5c) for storing the mutual information; and access changing portion (5d) responsive to the read instruction (2) for switching an access target such that the access target is the disc (7) when the read instruction (2) is directed to the data recorded on the disc ( 7), and that the access target is the internal storage (5c) when the

Abstract: In a central processing unit, there are provided a address register for storing source and destination addresses and a count register for storing a length of a block data transfer. The address and count registers are wholly or partly composed of a wide use register having other functions. Therefore, the number of registers is minimized.

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Abstract: Signal transmission method and apparatus is an input unit for inputting signals through operation of keys. Addresses of the operated keys are extracted through scanning and sent to a signal processing unit, while signals from the signal processing unit are subsequently received. For allowing the scanning to be performed even at the times of signal sending and reception, the scanning period is divided into a number of intervals equal to the numbers of bits which constitute the signal to be transmitted, wherein the sending and reception of the signal to be transmitted are performed in synchronism with the scanning intervals.

Abstract: An apparatus for reading data from a memory in a computer system includes: an address register for holding an address to be supplied to the memory, a read data register for holding data read out from the memory and a device for generating a gated clock signal from a free-running clock signal having a predetermined constant period of time. The gated clock signal is free-running with the predetermined constant period of time in a normal clock mode but is generated by a single pulse with an interval longer than the period of the free-running clock signal in a single clock mode. A device, having serially connected plural registers for shifting a trigger signal in accordance with the free-running clock signal generates a read data clock signal. The trigger signal has a same timing synchronized with a specific phase of the gated clock signal at which a phase of the address register is switched to hold a new address to be supplied to the memory.

Abstract: A parallel storage allocation method and device in which each space in a memory section that is available for use is associated with a respective allocator and stores an identifier for the respective allocator, data identifying allocators not in use is stored, and a list of allocators associated with spaces which are available for use is maintained. Each time a memory space is no longer in use a check is made to determine the allocator identifier of any already free space which can be combined with the memory space that is no longer in use. A liberate space token is generated which includes a first identifier corresponding to an allocator which is not in use and a second identifier which corresponds to any already free space to be combined. If the list of allocators relative to available space does not contain the allocator having the second identifier, the allocator having the first identifier is entered in the list with details of the no longer in use space.

Abstract: A memory mapper for an emulation system suitable for a microprocessor-based system for any size microprocessor is disclosed which uses function code comparators, range comparators, and offset values for individual mapping definitions, thereby providing faster mapping of emulation memory with higher resolution and flexibility in making changes. A single mapper cell is used for implementing each separate mapping definition. The function code comparator for the mapper cell defines the type of memory, the range comparator defines the section of memory covered by the mapper definition, and a translator is used to translate the original address to a translated address by adding an offset to the original address. Original addresses which do not match any mapper cell definitions are mapped according to a default definition.

Abstract: A system for providing input to a computer comprises a touchscreen apparatus for generating a grid of horizontal and vertical light beams and producing a set of output signals, each indicating whether a corresponding one of the light beams strikes an object. A scanning device repeatedly scans the states of the output signals, stores data representing the last scanned state of each output signal, and transmits a first interrupt signal to the computer whenever the state of any one of the output signals changes. In response to the interrupt signal, the computer reads the stored scan data, determines whether the data indicates that a horizontal and a vertical light beam is striking an object, and if so, sets parameter values to identify the horizontal and vertical light beams.

Abstract: An information processing apparatus with an address extension function includes a set of address adders for performing address addition with respect to a first fraction of an address for an instruction and/or a data, which fraction corresponds to the not extended bit portion of the address, and a set of domain registers for storing a second fraction of the address for an instruction or an operand, which fraction corresponds to the extended bit portion of the address. If address extension is not made, address translation into a real address is performed using a virtual address obtained through addition operation by the address adder and in accordance with a conventional not address extended program. If address extension is made, address translation into a real address is performed using a virtual address obtained by concatinating the addition result by the address adder with the content of the domain register.

Abstract: In accordance with one illustrated embodiment herein, a personal computer system such as that known as the PC/AT is adaptable by means of its expansion slots so as to provide a multichannel communications capability, with a plug-in communications board providing interrupt vectors to the mother board of the personal computer. A communications distribution configuration for the communications channels does not enlarge the footprint of the system or detract from its appearance. As many as eight communications lines are connectable with the illustrated distribution configuration in a neat and orderly fashion.

Abstract: The movement of a set of element data in a computer is achieved by a plurality of vector registers and a moving unit which can move a set of element data from one vector register to another register in response to one instruction without going through either main memory or the functional units. A selector responds to the instruction to route the output from one register to the input of another and to also provide the appropriate read and write starting addresses.

Abstract: A translation method for a machine translation system provided with apparatus for parsing a source language sentence and for forming a target language translation in which a phrase omitted in the source language setence is identified, and a word or phrase to be inserted for the omitted phrase is selected from stored words and phrases. For identifying an omitted phrase, a sentence pattern corresponding to a predicate in the source language sentence is formed so as to include not only cases governed by the predicate but also a semantic feature for each case. By comparing the source language sentence with the sentence pattern, a case which is omitted in the source language sentence but cannot be omitted in the target language translation is identified.

Abstract: An IC card has a CPU, a first memory for storing a test program, a second memory for storing an application progam, a bus connecting the CPU and the first and second memories. A detection circuit for detecting whether the CPU has began executing the application program stored in the second memory, and a disconnection circuit for disconnecting the first memory from the bus when the detection circuit detects that the CPU has begun executing the application program. The above-described arrangement makes it impossible to access the test program in the system ROM from the application program thereby preventing the occurrence of incorrect access.

Abstract: A method for storing into a non-EX cache line in a multiprocessor system. Upon a store into a non-EX line the instruction execution and the processing of subsequent instructions will continue. The results of the current instruction, however, and any subsequent instruction whose decode and execution depends upon the result of the current instruction or that requires operand fetches, will not be released until the processing of the current instruction is resolved. The request to store into the non-EX line is simultaneously sent to the SCE to obtain the EX state for the line. The SCE serializes storage requests. When a request for EX state is processed, certain XI actions (e.g. XI-invalidates) may be invoked. Any instruction using fetched data XI-invalidated before the resolution of a preceding store at the same CP is considered likely to be invalid, and redone.

Abstract: A method is provided to prevent continued unauthorized use of protected software and to maintain control of sites where software is installed. The method allows unauthorized copies of the protected software to be installed and to operate for a limited time. However, if the user does not register the software within a prescribed period of time, the protected software will be disabled. Prior to disabling, the software will operate for a period of time during which messages are provided to the user, warning that the software should be registered. Both a counter for counting the number of times that the protected software is used, and a timer for measuring the elapsed time since installation of the software, are used in determining how long the protected software will be permitted to operate before either registration or disabling.

Abstract: This invention speeds up the execution of instructions in an information processing system by tightly coupling two or more processors to a random access storage mechanism in such a manner that no arbitration is required and no processor is forced to wait while another processor accesses the storage mechanism. This is accomplished by coupling the processors to the storage mechanism in a time multiplexed manner which enables each processor to have a periodic regularly occurring turn at accessing the storage mechanism.

Abstract: A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.

Abstract: A bi-directional communication and control system includes a common network line over which messages are transmitted in a specific message format and a plurality of hardware based digital IC's which are coupled to the common network line and are arranged to receive messages from and transmit messages to the network line in the specific format is taught. Specifically, a multipurpose two-way communication device is taught which is connected to one of the digital ICs, the device being operable in a master mode in which the device interfaces an external controller to the network line through the connected digital IC so that the external controller can act as the master controller for the plurality of digital ICs coupled to the common network line.

Abstract: A method and mechanism operate for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.