Abstract: A single chip serial communications controller, adapted for transfer of data to memory in a direct memory access interrupt, generates a status word for each frame of data. To allow for uninterrupted transfer of data to memory from frame to frame, the status words are stored in a FIFO along with word counts corresponding to the frames to allow for subsequent identification of the addresses to which the data frames are assigned. The FIFO is incremented at the end of each frame and decremented as each status word is read by a CPU.

Abstract: A computer has a software trap handling pointer for holding the storing location of the information saved in the memory. At the setting of a software trap, the information containing the content of the software trap handling pointer is saved in the memory by means of a stack mechanism, and a value indicating the saved location is stored in the software trap handling pointer. At the time of a software trap return, the information containing the content of the software trap handling pointer which has been stored at the setting of the software trap is restored by means of the stack mechanism.

Abstract: In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.

Abstract: In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits.

Abstract: A processor node providing exclusive read-modify-write operations in a computer system having multiple processors interconnected by a pended bus and employing multiple lock bits. The processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O mode. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the command transfer. The command transfer, including an interlock read command, is stored in an input queue in memory and is processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue.

Abstract: In a data processing system, a measurement of the cumulative time used in the performance of an intermittent activity can be required. To determine this cumulative time, a memory location is designated during initialization that is to contain the value of the system clock determined at each initiation of the intermittent activity. A second memory location is provided during initialization that is to contain the accumulated total of the measurements taken to perform the intermittent activity. At each termination of the intermittent activity, the contents of the first and second locations are retrieved from the main memory. The value stored in the first main memory location is then subtracted from the system clock value at the termination of the current intermittent activity and the resulting value is added to the contents of the second location. The resulting value of the addition operation is then stored in the second main memory location.

Abstract: A memory management unit suitable for use in a digital signal processor has internal and eternal memories is described. The unit is especially designed to facilitate numeric algorithms such as fast fourier transforms, auto-correlation and digital filtering by relieving the programmer from the need to moniter memory accesses. Automatic post-updating of memory addresses is provided after indirect memory references. Also, memory boundary-checking is performed according to a user-specified modulus value, and a memory reference is automatically adjusted to fall within the user-specified address range. A dual-access register file stores initial memory addresses and their associated modulus values and in a dual-bus embodiment a pair of address generation units provides post-updates of the addresses stored in the register files.

Abstract: A network communications adapter interconnects a plurality of digital computing resources for mutual data exchange in which a high performance, large capacity common memory is provided with a pair of external buses which allows multiple processors to store information in and read information from the common memory. The common memory is configured into two banks, each bank operating independently and concurrently under control of bus switching logic with separate address, control and data buses. The common memory typically provides 400 megabits per second of bandwidth to the multiple attached thirty-two and sixteen bit processors which may be coupled either to both buses simultaneously or individually to the two buses. The bus switching logic then allocates all of the available bandwidth to the individual processors coupled to the buses based upon a predetermined profile established at the time of system installation. Also included in the bus switch logic is circuitry for broadcasting a processor I.D.

Abstract: In an input/output control system: a read/write operation for a control register (REG) under a program mode is achieved by hardware; the system is started or stopped under the control of firmware, and a data transfer in the system is achieved under the control of hardware. Therefore, a high speed data communication is realized, via the system, between a central control unit (CC) and an input/output unit (IO).

Abstract: A personal computer system includes a main circuit board having a central processing unit and expansion slots each of which is adapted to receive a printed circuit board card. The main circuit board further includes memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, which is substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The computer system reserves 256-megabytes of memory space ranging from location $X000 0000 to location $XFFF FFFF for memory on a card in a slot having a distinct number equal to $X.

Abstract: A computer system clock generator generates several system clock signals which are in a tuned state at desired locations, thereby offsetting the effects of varying propagation delays among the system clock signals. A shift register ring has one of its taps selectively connected to its data input so that a series of logic high level and logic low level data is advanced through the shifting stages. A tap selector for each desired output signal logically combines the signals output from the appropriate taps to produce output clock signals having desired leading and trailing edges.

Abstract: A method prevents an incorrect program version from being executed by a computer system. More specifically, a synchronization key is contained in a load module and is used to encrypt that load module which also contains a protected program. The encrypted load module with the protected program and synchronization key therein is stored in auxiliary storage. The synchronization key and program name are then placed in a table in a secure memory. When the program is requested for execution, the synchronization key in the protected table corresponding to the program name is used to decrypt the load module. The synchronization key in the load module is then extracted and compared with the synchronization key which is stored in a protected table and associated with the protected program. If the two synchronization keys are the same, then the decrypted protected program is loaded into the main memory for execution.

Abstract: A microcomputer has an instruction memory and a high-speed sense amplifier and can selectively operate according to a high-speed operation mode and to a low-speed operation mode. The high-speed sense amplifier is activated in a full time or with a large duty rate in the high-speed operation mode and is activated with a short duty rate in the low-speed operation mode.

Abstract: A data sharing mechanism employs a broadcast bus communication system to physically interconnect various control and monitoring nodes that cooperate in controlling a physical process. Shared, or global, variables are exchanged between connected nodes via a global data service provider and protocol. The protocol allows global variables to be addressed by symbolic names with multiple namespaces for the names. Additionally, the protocol allows data to be formatted with special identifiers such that once a variable name has been located in a message from a specified source, and other messages from that source with the same identifier are received, they will have the named variables in the same relative locations. The receiver can therefore directly index to the named variable when the source and identifier are known.

Abstract: An instruction code access control system used in an instruction code prefetched computer system includes at least an instruction buffer for accumulating prefetched instruction codes, and a data path switch for selectively coupling the instruction buffer to a data path through which an instruction code and an operand data are selectively transferred. The system also comprises a fetch counter for counting the number of the instruction codes accumulated in the instruction buffer from the time a discontinuous program control is carried out. There is provided a counter detector for comparing the value of the fetch counter with a predetermined value. An arbiter is provided for determining, on the basis of the output of the counter detector, a priority between an instruction memory access for instruction code prefetching and an operand access caused as the result of an instruction execution. The arbiter operates to control the data path switch in accordance with the result of the determination.

Abstract: A computer system includes a central processing unit, a main memory unit and a master controller unit, which master controller interconnects the processing unit and the memory. The processing unit utilizes virtual addresses and generates virtual address to access the memory. However, the memory is accessed using real addresses. Thus, the master controller performs the required translating function for the interoperability of the processor and memory and does so without requiring instructions from the processor. This represents a significant decrease in processor overhead.

Abstract: A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.

Abstract: Buffer memory overflow control is realized by controlling the amount of packet data being inputted to the buffer memory in response to the amount of packet data stored in the buffer memory. Depending on the type of coding being employed and the amount of data stored in the buffer memory, one or more groups of bits are controllably dropped from the packet information field being inputted into the buffer memory.

Abstract: A memory device provided on a one-chip microcomputer includes a high-speed ROM and a low-speed ROM which are arranged in the same address space and thus can be addressed by the same address pointer, wherein information requiring a high-speed operation and/or having a high access frequency is stored in the high-speed ROM and information requiring no high-speed operation and/or low access frequency is stored in the low-speed ROM. Another memory includes a pair of first and second memories, wherein the first memory includes an extended instruction for accessing the second memory, which thus serves as a virtual memory. The second memory is accessed only when reference is made to an address of an operand of an instruction which immediately follows the extended instruction.

Abstract: A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.