Abstract: Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

Abstract: An image sensor includes a first light sensor layer including light sensing cells configured to sense first light of an incident light and generate electrical signals based on the sensed first light, and a color filter array layer disposed on the first light sensor layer, and including color filters respectively facing the light sensing cells. The image sensor further includes a second light sensor layer disposed on the color filter array layer, and configured to sense second light of the incident light and generate an electrical signal based on the sensed second light. Each of the color filters includes a nanostructure including a first material having a first refractive index, and a second material having a second refractive index greater than the first refractive index, the first material and the second material being alternately disposed with a period.

Abstract: An organic light-emitting device having low-driving voltage, improved efficiency, and long lifespan includes: a first electrode; a second electrode facing the first electrode; a first layer between the first electrode and the second electrode, the first layer including a first compound; a second layer between the first layer and the second electrode, the second layer including a second compound; and a third layer between the second layer and the second electrode, the third layer including a third compound; wherein the first compound does not include a nitrogen-containing heterocyclic group comprising *?N—*? as a ring forming moiety, and wherein the first compound, the second compound, and the third compound each independently include at least one group selected from groups represented by Formulae A to C:

Abstract: A semiconductor device includes: a first board that has a first end surface and a second end surface opposite to the first end surface; a second board that is attached to the second end surface of the first board; a plurality of first electrodes that are provided on the first end surface; a second electrode that is provided on the second end surface and electrically coupled to an electrode of the second board; an internal wiring that is provided inside the first board and electrically coupled to the second electrode; a plurality of third electrodes that are provided inside the first board and electrically couple the first electrodes to the internal wiring; and a strain sensor that is provided inside the first board and measures a strain generated in the first board, in which a linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the first board.

Abstract: A display apparatus is provided including a display area and a non-display area. The display area includes a display element and the non-display area includes a pad portion. A first thin-film transistor (TFT) is arranged in the display area. The first TFT includes silicon and a first gate electrode. A second TFT is arranged on a first insulating layer covering the first gate electrode and includes an oxide and a second gate electrode. A first voltage line extends in a first direction. A data line is spaced apart from the first voltage line. A connection wire is disposed in the display area and connects the data line to the pad portion. The connection wire includes a first portion extending in the first direction and a second portion extending in a second direction crossing the first direction, and the first portion overlaps the first voltage line.

Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.

Abstract: A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

Abstract: An organic light emitting diode display includes: a substrate; a scan line formed over the substrate and transmitting a scan signal; a data line crossing the scan line and transmitting a data voltage; a driving voltage line crossing the scan line and transmitting a driving voltage; a switching transistor connected to the scan line and the data line; a driving transistor connected to the switching transistor; a driving connection member connected to a driving gate electrode of the driving transistor; a storage capacitor including a first storage electrode and a second storage electrode; a pixel electrode electrically connected to the driving transistor; and a contact hole connecting the first storage electrode and the driving connection member. The second storage electrode may include a cut-out by a curved edge at least partially surrounding the contact hole, and the pixel electrode may be formed not to overlap the cut-out.

Abstract: Microbolometer systems and methods are provided herein. For example, an infrared imaging device includes a substrate having contacts and a surface. The surface defines a plane. The infrared imaging device further includes a microbolometer array coupled to the substrate. Each microbolometer of the microbolometer array includes a second having a first dimension that extends in a first direction substantially parallel to the plane and a second dimension that extends in a second direction away from the plane. The first dimension is less than the second dimension. The segment includes a metal layer and a layer formed on a side of the metal layer.

Abstract: An image sensor is provided to include an active region which comprises: a floating diffusion region; a transfer transistor gate region; transistor active regions; and a well-tap region. The transfer transistor gate region may have a diagonal bar shape to isolate the floating diffusion region in a first corner of the active region. The well-tap region may be positioned between the transfer transistor gate region and the transistor active regions, and isolate the transfer transistor gate region from the transistor active regions.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating transistors. In one aspect, a transistor includes: (1) a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and (2) a superconducting component configured to operate in a superconducting state while: (a) a temperature of the superconducting component is below a superconducting threshold temperature; and (b) a first current supplied to the superconducting component is below a current threshold; where: (i) the semiconducting component is located adjacent to the superconducting component; and (ii) in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

Abstract: A semiconductor assembly includes a semiconductor component having a redistribution substrate with a top side, an underside and a semiconductor chip on the top side. Contact connection pads for connection to contact pads of the chip are on the top side of the substrate. External contact pads on the underside are electrically connected to the contact connection pads by conductor tracks. The external contact pads are at a greater distance from one another in a first region than a second region of the underside. The semiconductor component is on a printed circuit board. Contact pads corresponding to the external contacts are on a top side of the printed circuit board and are at a greater distance from one another in a first region than a second region of the top side. Through holes are formed between the contact pads in the first region of the printed circuit board.

Abstract: A semiconductor package includes a processor, a lower memory including a plurality of lower memory chips that are vertically stacked, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer, the upper memory including a plurality of upper memory chips that are vertically stacked. The interposer includes a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory, and the processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.

Abstract: A display device includes a base substrate in which a display area and a pad area disposed around the display area are defined, a plurality of panel pads disposed on the pad area of the base substrate, and a printed circuit board attached to the pad area of the base substrate. The printed circuit board includes a plurality of circuit pads, the plurality of circuit pads include a first lead align mark, and the first lead align mark includes a plurality of first patterns passing through the first lead align mark from a surface of the first lead align mark in a thickness direction.

Abstract: A process and apparatus is provided in which improved control of gas phase radicals is provided. In one embodiment, a system generating atomic oxygen is provided in which gases which generate the atomic oxygen are mixed prior to injection in a process space. The mixing may occur within a showerhead or prior to entrance into the showerhead. In another embodiment, a showerhead is provided which includes multiple zones. Some of the zones of the showerhead may inject the mixture of gases which generate the atomic oxygen into the process space, while other zones do not inject that mixture. In one embodiment, the mixture of gases which generates the atomic oxygen is injected into a main zone, while a subset of those gases is injected into inner and outer zones of the showerhead. The process and apparatus provides a uniform density of atomic oxygen across the substrate being processed.

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

Abstract: A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface t

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.