Patents Examined by Benjamin Tzu-Hung Liu
  • Patent number: 11282725
    Abstract: A wafer transfer unit includes at least one data processing unit, which is configured at least for a registration and/or processing of sensor data of at least one sensor, allocated to at least one sub-component of a wafer transfer system, of a sensor module, in particular includes at least one wafer processing module of the wafer transfer system, includes at least one wafer interface system of the wafer transfer system with a wafer transport container and a loading and/or unloading station for a loading and/or unloading of the wafer transport container and/or of the wafer processing module, includes at least one wafer transport container transport system of the wafer transfer system and/or includes at least one wafer handling robot of the wafer transfer system.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 22, 2022
    Assignee: VAT Holding AG
    Inventors: Florian Ehrne, Martin Netzer, Andreas Hofer, Eligio Belleri, Marco Apolloni, Thomas L. Swain
  • Patent number: 11282788
    Abstract: A structure (interconnect or memory structure) is provided that includes a first electrically conductive structure having a concave upper surface embedded in a first interconnect dielectric material layer. A metal-containing cap having a convex bottom surface directly contacts the concave upper surface of the first electrically conductive structure. A metal-containing structure having a planar bottommost surface directly contacts a planar topmost surface of the metal-containing cap. A second electrically conductive structure contacts the planar topmost surface of the metal-containing structure. A second interconnect dielectric material layer is present on the first interconnect dielectric material layer and is located laterally adjacent to an upper portion of the metal-containing cap, the metal-containing structure, and the second electrically conductive structure.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li
  • Patent number: 11283012
    Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 22, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: R. Stanley Williams
  • Patent number: 11274370
    Abstract: A process and apparatus is provided in which improved control of gas phase radicals is provided. In one embodiment, a system generating atomic oxygen is provided in which gases which generate the atomic oxygen are mixed prior to injection in a process space. The mixing may occur within a showerhead or prior to entrance into the showerhead. In another embodiment, a showerhead is provided which includes multiple zones. Some of the zones of the showerhead may inject the mixture of gases which generate the atomic oxygen into the process space, while other zones do not inject that mixture. In one embodiment, the mixture of gases which generates the atomic oxygen is injected into a main zone, while a subset of those gases is injected into inner and outer zones of the showerhead. The process and apparatus provides a uniform density of atomic oxygen across the substrate being processed.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 15, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Anthony Dip
  • Patent number: 11270964
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Christopher D. Muzzy
  • Patent number: 11270935
    Abstract: A method of forming cut conductive lines is provided. The method includes forming a trough in a dielectric cover layer over a plurality of electrical contacts. The method further includes filling the trough with a planarization layer, and forming a plurality of vias in the planarization layer and the dielectric cover layer, wherein each of the plurality of vias is aligned with one of the plurality of electrical contacts. The method further includes removing the planarization layer, and forming a sacrificial via plug in each of the plurality of vias in the dielectric cover layer. The method further includes forming a fill layer in the trough, and forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs. The method further includes forming a separator in the planarization layer opening.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Chih-Chao Yang, Jing Guo
  • Patent number: 11264553
    Abstract: An overheat detection system and insulation muff comprising an overheat detection system. The overheat detection system comprises a thermometer, a thermal harvesting module comprising at least one passive radiator, the thermal harvesting module being able to generate electrical energy from the thermal difference between two elements, and a digital module, comprising a power management system, a data treatment system and a wireless transmission system, wherein the electrical energy generated by the thermal harvesting module powers the thermometer and the digital module.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 1, 2022
    Assignee: AIRBUS OPERATIONS S.L.
    Inventors: Brice Lenoir, Panagiotis Mourtis Ioannou
  • Patent number: 11264315
    Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Jiun Hann Sir, Hoay Tien Teoh, Jimmy Huat Since Huang
  • Patent number: 11239123
    Abstract: A base plate (1) includes a fixed surface and a radiating surface which is a surface opposite to the fixed surface. An insulating substrate (3) is bonded to the fixed surface of the base plate (1). Conductive patterns (4,5) are provided on the insulating substrate (3). Semiconductor chips (7,8) are bonded to the conductive pattern (4). An Al wire (12) connects top surfaces of the semiconductor chip (8) to the conductive pattern (5). The insulating substrate (3), the conductive patterns (4 ,5), the semiconductor chips (7 to 10) and the Al wires (11 to 13) are sealed with resin (16). The base plate (1) includes a metal part (19) and a reinforcing member (20) provided in the metal part (19). A Young's modulus of the reinforcing member (20) is higher than a Youngs modulus of the metal part (19).
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: February 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuya Kawase, Noboru Miyamoto, Mikio Ishihara, Junji Fujino, Yuji Imoto, Naoki Yoshimatsu
  • Patent number: 11227982
    Abstract: An LED package creates a narrow beam in a very compact package without use of a lens. A plastic is molded around a metal lead frame (12, 14) to form a molded cup (26), where the cup has parabolic walls extending from a bottom area of the cup to a top thereof. The lead frame forms a first set of electrodes exposed at the bottom area of the cup for electrically contacting a set of LED die electrodes (18, 20). The lead frame also forms a second set of electrodes outside of the cup for connection to a power supply. A reflective metal (28) is then deposited on the curved walls of the cup. An LED die (16) is mounted at the bottom area of the cup and electrically connected to the first set of electrodes. The cup is then partially filled with an encapsulant (64) containing a phosphor (66).
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 18, 2022
    Assignee: Lumileds LLC
    Inventor: Mark Melvin Butterworth
  • Patent number: 11222842
    Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin
  • Patent number: 11217721
    Abstract: Provided is a light-emitting device that includes a first electrode layer, a first conduction type layer, a second conduction type layer, an active layer, and a second electrode layer. The first conduction type layer includes a current injection region formed by the first electrode layer and a current non-injection region. A waveguide structure included in the first conduction type layer, the active layer, and the second conduction type layer includes a first region and a second region. The first region has a first waveguide that is the current injection region and the current non-injection region and has a first refractive index difference. The second region has a second waveguide arranged to be extended from the first waveguide to the first end and has a second refractive index difference greater than the first refractive index difference. The second waveguide has a region narrowing toward the first end.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 4, 2022
    Assignee: SONY CORPORATION
    Inventors: Kentaro Fujii, Tomoki Ono, Yoshiaki Watanabe
  • Patent number: 11208320
    Abstract: A MEMS microphone includes a substrate defining a cavity including a first sidewall extending a vertical direction, a back plate disposed over the substrate and defining a plurality of acoustic holes, a diaphragm disposed between the substrate and the back plate, the diaphragm having at least one vent hole, an anchor extending from a circumference of the diaphragm to connect an end portion of the diaphragm to an upper surface of the substrate, and at least one path member communicating with the vent hole, the path member providing a flow path for the acoustic pressure to flow downwardly toward the cavity.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 28, 2021
    Assignee: DB HITEK CO., LTD.
    Inventors: Dae Young Kim, Jin Hyung Lee
  • Patent number: 11211564
    Abstract: An organic light-emitting device having low-driving voltage, improved efficiency, and long lifespan includes: a first electrode; a second electrode facing the first electrode; a first layer between the first electrode and the second electrode, the first layer including a first compound; a second layer between the first layer and the second electrode, the second layer including a second compound; and a third layer between the second layer and the second electrode, the third layer including a third compound; wherein the first compound does not include a nitrogen-containing heterocyclic group comprising *?N—*? as a ring forming moiety, and wherein the first compound, the second compound, and the third compound each independently include at least one group selected from groups represented by Formulae A to C:
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seulong Kim, Younsun Kim, Dongwoo Shin, Jungsub Lee, Naoyuki Ito, Jino Lim
  • Patent number: 11211583
    Abstract: The encapsulation structure includes a first barrier layer and a second barrier layer, and the first barrier layer is located between an object to be encapsulated and the second barrier layer. The display panel includes the encapsulation structure mentioned in the above technical solution. The display apparatus includes the display panel mentioned in the above technical solution.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 28, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dawei Wang, Youwei Wang
  • Patent number: 11195778
    Abstract: An electronic power module, including at least one semiconductor component, which is arranged on a support, as well as a cooling element, which is in thermal contact with the semiconductor component, wherein the support includes a semiconductor material and, at the same time, serves as a cooling element.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: December 7, 2021
    Assignees: AUDI AG, ABB Schweiz AG
    Inventors: Andreas Apelsmeier, Günter Vetter
  • Patent number: 11183670
    Abstract: An organic light emitting diode (OLED) device includes an emissive layer having a first sublayer with a first emitter as a dopant, a second sublayer with a second emitter as a dopant, and a third sublayer with a third emitter as a dopant. The second sublayer is between the first sublayer and the third sublayer. A concentration of the first emitter in the first sublayer exceeds a concentration of the third emitter in the third sublayer, and the concentration of the third emitter in the third sublayer exceeds a concentration of the second emitter in the second sublayer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 23, 2021
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Jian Li, Kody George Klimes
  • Patent number: 11177438
    Abstract: An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 16, 2021
    Assignee: Tetramen Inc.
    Inventors: Minxian Zhang, Ning Ge
  • Patent number: 11177273
    Abstract: A nonvolatile memory device includes a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors. The row line voltage is supplied through a plurality of row lines connecting the pass transistors to the memory cell array. Each of the row lines includes a wiring line parallel with a main surface of the substrate and a contact perpendicular to the main surface of the substrate. The wiring line of at least one row line among the row lines includes a plurality of conductive lines.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: November 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sung-Hoon Kim
  • Patent number: 11150495
    Abstract: A technique is described to deterministically tune the emission frequency of individual semiconductor photon sources, for example quantum dots. A focused laser is directed at a film of material that changes form when heated (for example, a phase change material that undergoes change between crystal and amorphous forms) overlaid on a photonic membrane that includes the photon sources. The laser causes a localized change in form in the film, resulting in a change in emission frequency of a photon source.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 19, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Joel Q. Grim, Allan S. Bracker, Samuel Carter, Daniel Gammon