Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.

Abstract: A magnetic light-emitting structure and fabrication method for manufacturing a magnetic light-emitting element are provided. The fabrication method comprises providing a magnetic metal composite substrate, wherein a second metal layer is respectively disposed on an upper and lower surface of a first metal layer; forming a connecting metal layer, an epitaxial layer and a plurality of electrode unit on top; and performing a complex process, which removes the second metal layer on the lower surface of the first metal layer and part of the first metal layer and performs cutting according to the number of the electrode unit, so as to form a plurality of epitaxial die. Each epitaxial die corresponds to an electrode unit to form a magnetic light-emitting element. The proposed method improves soft magnetic properties of an original substrate and enables dies to reverse spontaneously, thereby used perfectly for industrial mass transfer technology.

Abstract: A light-emitting module includes (i) a board provided with: a circuit pattern and a plurality of bottomed holes in each of a set of wiring pads continuous with the circuit pattern on a first surface; electrically conductive paste extending over two or more of the bottomed holes; and an insulating resin covering the electrically conductive paste at a side close to the first surface, and (ii) a plurality of light-emitting segments connected to a second surface of the board with an adhesive sheet interposed therebetween. The light-emitting segments each include a plurality of light-emitting devices that are aligned. The electrically conductive paste includes a portion disposed on a portion of a surface of the wiring pad extending over two or more of the bottomed holes.

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

Abstract: A micro light emitting diode (LED) transferring method includes setting a micro LED transfer substrate and a target substrate to initial positions and transferring a plurality of micro LEDs arranged in a partial region of the micro LED transfer substrate to the target substrate. Once the micro LEDs in the partial region are transferred to the target substrate, the micro LED transfer substrate is rotated and a plurality of micro LEDs, arranged in a remaining region of the micro LED transfer substrate, are then transferred to the target substrate.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

Abstract: Various systems and methods of initiating and performing contextualized AI inferencing, are described herein. In an example, operations performed with a gateway computing device to invoke an inferencing model include receiving and processing a request for an inferencing operation, selecting an implementation of the inferencing model on a remote service based on a model specification and contextual data from the edge device, and executing the selected implementation of the inferencing model, such that results from the inferencing model are provided back to the edge device. Also in an example, operations performed with an edge computing device to request an inferencing model include collecting contextual data, generating an inferencing request, transmitting the inference request to a gateway device, and receiving and processing the results of execution. Further techniques for implementing a registration of the inference model, and invoking particular variants of an inference model, are also described.

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

Abstract: A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.

Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

Abstract: Method and calculating unit for curve sawing of a block in a cutting direction with at least a first circular saw blade. The method comprises determining a radius of the curve sawing, by measuring the curvature of the block in the direction of cutting; calculating a vertical inclination angle of the first circular saw blade in a vertical plane relative to the cutting direction in the block, based on the determined radius of the curve sawing; inclining the first circular saw blade with the calculated vertical inclination angle; and sawing the block in the cutting direction with the inclined first circular saw blade along the determined radius of the curve sawing.

Abstract: A method for transferring a thin layer onto a destination substrate having a face with an adhesive layer includes formation of a polymer material interface layer on a second face of a thin layer, opposite a first face on which an adhesive is present. The method also includes assembly by gluing the interface layer and the adhesive layer and separation of the thin layer relative to a temporary support.

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

Abstract: A mass transfer method includes providing a transfer unit and a semiconductor carrying unit connected therewith, removing an element supporting structure of the semiconductor carrying unit from micro semiconductor elements of the semiconductor carrying unit, partially removing the photosensitive layer to form connecting structures, connecting a package substrate with electrodes of the micro semiconductor elements, breaking the connecting structures to separate the micro semiconductor elements from the transfer substrate. A mass transfer device is also disclosed.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; depositing a conductive material to partially fill the trench; and forming an insulative piece in the trench and extending into the conductive material.

Abstract: A lift-off method includes a relocation substrate joining step of joining a relocation substrate to a surface of an optical device layer of an optical device wafer with a joining member interposed therebetween, thereby forming a composite substrate, a buffer layer breaking step of applying a pulsed laser beam having a wavelength transmittable through an epitaxy substrate and absorbable by a buffer layer to the buffer layer from a reverse side of the epitaxy substrate of the optical device wafer of the composite substrate, thereby breaking the buffer layer, and an optical device layer relocating step of peeling off the epitaxy substrate from the optical device layer, thereby relocating the optical device layer to the relocation substrate. In the buffer layer breaking step, irradiating conditions of the pulsed la-ser beam are changed for respective ring-shaped areas of the buffer layer, and the pulsed laser beam is applied to the optical device wafer under the changed irradiating conditions.

Abstract: A semiconductor wafer according to the present embodiment is a semiconductor wafer having a first face. A plurality of chip structures are provided on a plurality of chip regions of the first face. A test structure is provided on dicing regions between adjacent ones of the chip regions. The chip structures each comprise first integrated circuits provided on the semiconductor wafer, and a first stacked body provided above the first integrated circuits and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked. The test structure comprises second integrated circuits provided on the semiconductor wafer, and a second stacked body provided above the second integrated circuits and including the first layers and the second layers alternately stacked.

Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.