Abstract: A light-emitting element includes: pixel electrodes provided for individual subpixels of at least three colors; a common electrode provided facing each of the pixel electrodes; and light-emitting layers of each color provided between the common electrode and, respectively, each of the pixel electrodes, wherein one of each of the pixel electrodes and the common electrode is a cathode electrode and the other is an anode electrode and among the light-emitting layers of the at least three colors, a light-emitting layer of a color having a largest electron affinity extends in a state of being layered between the cathode electrode and each light-emitting layer of the other colors as well.

Abstract: An array substrate, a method for preparing the array substrate, and a backlight module are disclosed. Before electroplating a first metal layer on a pattern of a seed layer, the method further includes: forming a pattern of a compensation electrode wire electrically connected with a lead electrode on a side, where the lead electrode is formed, of a base substrate. The compensation electrode wire is at least on a second side of a wiring region, the pattern of the lead electrode is formed at a first side of the wiring region, and the first side and the second side are different sides. In the electroplating process, the lead electrode is connected with a negative pole of a power supply, the compensation electrode wire is electrically connected with the lead electrode, thus an area of an electroplating negative pole generating electric field lines is increased by utilizing the compensation electrode wire.

Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.

Abstract: Electrostatic chucks (ESCs) for plasma processing chambers, and methods of fabricating ESCs, are described. In an example, a substrate support assembly includes a ceramic bottom plate having heater elements therein. The substrate support assembly also includes a ceramic top plate having an electrode therein. A metal layer is between the ceramic top plate and the ceramic bottom plate. The ceramic top plate is in direct contact with the metal layer, and the metal layer is in direct contact with the ceramic bottom plate.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: A method of forming an electrical metal contact within a semiconductor layer stack of a vertical cavity surface emitting laser includes forming a contact hole into the semiconductor layer stack. The contact hole has a bottom and a side wall extending from the bottom. The method further includes providing a photoresist mask inside the contact hole. The photoresist mask covers the side wall of the contact hole and has an opening extending to the bottom of the contact hole. The method additionally includes wet-chemical isotropic etching the bottom of the contact hole, depositing a metal on the bottom of the contact hole, and removing the photoresist mask so that the metal on the bottom of the contact hole is left as the electrical metal contact.

Abstract: A photodetector for detecting deep ultra-violet light includes a substrate; first and second electrodes separated by a channel; and colloidal MnO based quantum dots formed in the channel. The colloidal MnO based quantum dots are sensitive to ultra-violet light having a wavelength lower than 300 nm.

Abstract: An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg1-xCdxTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

Abstract: A light-emitting diode package having a controlled beam angle is proposed. The diode package can include at least one first lead frame; at least one second lead frame formed to correspond to and be spaced apart from the at least one first lead frame; light-emitting diode chips mounted on the at least one first lead frame; a first package main body which is fixed on the partial surfaces of the at least one first lead frame and the at least one second lead frame and formed so as to have a first inclined side at a portion of the circumference around the light-emitting diode chips; and a second package main body formed so as to have a second inclined side at the remaining portion of the circumference around the light-emitting diode chips other than the portion.

Abstract: A heat dissipation sheet 10 includes cohesive inorganic filler particles 1 having a breaking strength of 20 MPa or lower and a modulus of elasticity of 48 MPa or higher and a matrix resin 2.

Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

Abstract: A vibration device includes a semiconductor substrate having a first surface and a second surface, an integrated circuit disposed on the first surface, a first terminal which is disposed on the second surface and to which a substrate potential is applied, a second terminal which is disposed on the second surface and to which a potential different from the substrate potential is applied, a first through electrode which is configured to electrically couple the first terminal and the integrated circuit to each other, a second through electrode which is configured to electrically couple the second terminal and the integrated circuit to each other, a frame which has an insulating property, a vibration element disposed on the first surface, and a lid bonded to the first surface, wherein the first through electrode is located outside the frame, and the second through electrode is located inside the frame.

Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.

Abstract: Semiconductor wafer devices are formed of a wafer or a portion of a wafer. The wafer or wafer portion includes a plurality of functional blocks, one of which comprises an energy source and another which takes some other form, such as digital logic, data storage, a communication module, a display, a display driver, or a sensor. A functional block may be formed as part of processing of the wafer or may comprise a post-processing element. The functional blocks combine to provide an operational system having a plurality of functions. The wafer may be formed of an amorphous material, allowing the device to have a three-dimensional, non-planar structure, such as a cuboidal or tubular structure. If the device comprises only a portion of a wafer, a plurality of devices may be formed from a single wafer, with each portion being removed from the remainder of the wafer to define a device.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating diodes. In one aspect, an electrical circuit includes: (1) a diode component having a particular energy band gap; (2) an electrical source electrically coupled to the diode component and configured to bias the diode component in a particular state; and (3) a heating component thermally coupled to a junction of the diode component and configured to selectively supply heat corresponding to the particular energy band gap.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.

Abstract: An optical sensor includes: a photosensitive layer that absorbs incident light to generate a first carrier with a first polarity and a second carrier with a second polarity different from the first polarity; a channel layer that is electrically connected to the photosensitive layer and that conducts the first carrier that has moved from the photosensitive layer; a counter electrode facing the channel layer through the photosensitive layer; an insulating layer positioned between the photosensitive layer and the counter electrode; and a source electrode and a drain electrode each electrically connected to the channel layer.