Abstract: A photoelectric device includes a first photoelectric conversion layer including a heterojunction that includes a first p-type semiconductor and a first n-type semiconductor, a second photoelectric conversion layer on the first photoelectric conversion layer and including a heterojunction that includes a second p-type semiconductor and a second n-type semiconductor. A peak absorption wavelength (?max1) of the first photoelectric conversion layer and a peak absorption wavelength (?max2) of the second photoelectric conversion layer are included in a common wavelength spectrum of light that is one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, a blue wavelength spectrum of light, a near infrared wavelength spectrum of light, or an ultraviolet wavelength spectrum of light, and a light-absorption full width at half maximum (FWHM) of the second photoelectric conversion layer is narrower than an FWHM of the first photoelectric conversion layer.

Abstract: The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.

Abstract: A design process is used for designing a device comprising a plurality of micro-machined elements, each comprising a flexible membrane, the elements being arranged in a plane in a determined topology. The design process comprises a step of defining the determined topology so that it has a character compatible with a generic substrate having cavities, the characteristics of which are pre-established. Each flexible membrane of the micro-machined elements is associated with one cavity of the generic substrate. The present disclosure also relates to a fabrication process for fabricating a device comprising a plurality of micro-machined elements, and to this device itself, wherein only some of the pairs of cavities and flexible membranes are configured to form a set of functional micro-machined elements.

Abstract: A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.

Abstract: Example embodiments relate to image sensors for time delay and integration imaging and methods for imaging using an array of photo-sensitive elements. One example image sensor for time delay and integration imaging includes an array of photo-sensitive elements that includes a plurality of photo-sensitive elements arranged in rows and columns of the array. Each photo-sensitive element includes an active layer configured to generate charges in response to incident light on the active layer. Each photo-sensitive element also includes a charge transport layer. Further, each photo-sensitive element includes at least a first and a second gate, each separated by a dielectric material from the charge transport layer. The array of photo-sensitive elements is configured such that the second gate of a first photo-sensitive element and the first gate of a second photo-sensitive element in a direction along a column of the array are configured to control transfer of charges.

Abstract: An apparatus for growing semiconductor wafers, in particular of silicon carbide, wherein a chamber houses a collection container and a support or susceptor arranged over the container. The support is formed by a frame surrounding an opening accommodating a plurality of arms and a seat. The frame has a first a second surface, opposite to each other, with the first surface of the frame facing the support. The arms are formed by cantilever bars extending from the frame into the opening, having a maximum height smaller than the frame, and having at the top a resting edge. The resting edges of the arms define a resting surface that is at a lower level than the second surface of the frame. The seat has a bottom formed by the resting surface.

Abstract: A photo transistor and a display device employing the photo transistor are provided. The photo transistor includes a gate electrode disposed on a substrate, a gate insulating layer that electrically insulates the gate electrode, a first active layer overlapping the gate electrode and including metal oxide, wherein the gate insulating layer is disposed between the gate electrode and the active layer, a second active layer disposed on the first active layer and including selenium, and a source electrode and a drain electrode respectively electrically connected to the second active layer.

Abstract: In a described example, an apparatus includes: a photon detector array with a first signal output pad coupled to a photon detector array pixel; a die carrier comprising a readout integrated circuit (ROIC) die and a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die; and the first signal output pad coupled to the first signal input pad.

Abstract: There are provided methods of growing arrays of light emitters on substrates. An example method includes adjusting a growth parameter of a given light emitter of an array of light emitters on a substrate to obtain an adjusted growth parameter. The adjusting may be based on a location of the given light emitter on the substrate. The adjusting may be to compensate for nonuniformity in a growth profile of the light emitters across the substrate. The nonuniformity may be associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters. Adjusting the growth parameter may be to adjust the corresponding nonuniformity. The method may also include growing the given light emitter on the substrate based on the adjusted growth parameter. Arrays of corresponding light emitters are also described.

Abstract: A display device includes pixel circuits disposed on a substrate, each of the pixel circuits comprising a transistor and a storage capacitor, display elements electrically connected to the pixel circuits, and a metal layer disposed between the substrate and the pixel circuits, the metal layer comprising through-holes, wherein the through-holes of the metal layer include a first through-hole, and a second through-hole disposed adjacent to the first through-hole.

Abstract: An integrated circuit is described herein that includes a semiconductor substrate. First and second piezoresistive sensors are on or in the substrate where each have a respective sensing axis extending in first and second directions respectively parallel with a surface of the substrate, where the second direction is perpendicular to the first direction. A third piezoresistive sensor is on or in the substrate and has a respective sensing axis extending in a third direction parallel with the surface of the substrate and neither parallel nor perpendicular to the first and second directions.

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: Exemplary methods of semiconductor processing may include providing a boron-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the boron-containing precursor and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a boron-and-carbon-containing layer on the substrate.

Abstract: A display device includes a display panel including a substrate including a front display region, a side display region extending from a side of the front display region, and a transmission region including at least a portion overlapping the front display region in a plan view; and a sensor located on a bottom of the substrate, the sensor having at least a portion overlapping the transmission region in a plan view. The display panel includes first pixels in the front display region; a load compensation element in the side display region; and a connection line electrically connecting the first pixels and the load compensation element by detouring the transmission region.

Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

Abstract: Aspects of the subject technology relate to an apparatus including a housing, one or more piezoresistive elements and a magnetic actuator. The housing includes a membrane, and the piezoresistive elements are disposed on the membrane to sense a displacement due to a deflection of the membrane. The magnetic actuator is disposed inside a cavity of the housing. The magnetic actuator exerts a repulsive force onto the membrane to reduce the deflection of the membrane.

Abstract: A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.