Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor, then the first initial doping level is reduced to a second initial doping level of the first or low second conductivity type.

Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate capable of being bent in a first direction and an insulating layer including a first opening pattern positioned on the flexible substrate and extending in a second direction crossing the first direction.

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper part of the air spacer.

Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

Abstract: A power semiconductor module includes: at least one semiconductor substrate having a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; at least one semiconductor body arranged on the first metallization layer; at least one end stop element arranged either on the semiconductor substrate or on one of the at least one semiconductor body and extending from the semiconductor substrate or the respective semiconductor body in a vertical direction that is perpendicular to a top surface of the semiconductor substrate; and a housing at least partly enclosing the semiconductor substrate, the housing including sidewalls and a cover. The housing further includes at least one press-on pin extending from the cover of the housing towards one of the at least one end stop element, and exerting a pressure on the respective end stop element.

Abstract: A structure includes an oriented piezoelectric polymer arranged in a circular tubular or circular columnar shape, wherein the orientation angle of the piezoelectric polymer with respect to the central axis of the structure is 15° to 75°, the piezoelectric polymer includes a crystalline polymer having an absolute value of 0.1 to 1000 pC/N for the piezoelectric constant d14 when the orientation axis is the third axis, and the piezoelectric polymer includes a P-body containing a crystalline polymer with a positive piezoelectric constant d14 value and an N-body containing a crystalline polymer with a negative value, wherein for the portion of the central axis of the structure having a length of 1 cm, the value of T1/T2 is 0 to 0.8, T1 being the smaller and T2 being the larger of (ZP+SN) and (SP+ZN), where ZP, SP, ZN, and SN are particularly defined masses.

Abstract: The present invention provides a method for testing performance of thin-film encapsulation. Through different combination designs of film layers, lateral water vapor intrusion paths of various thin films or encapsulation structures are formed, thereby obtaining a means to inspect a lateral water vapor and oxygen barrier capacity of thin films and provide a highly effective inspection means for encapsulation of display panels.

Abstract: An apparatus comprising a substrate, one or more nanowire pillars, each having a base portion and a tip portion, a first electrode connected to the tip portions of the one or more nanowire pillars, an internal hollow cavity positioned between the substrate and the first electrode, such that at least a portion of each of the one or more nanowire pillars extend through the internal hollow cavity, and a second electrode proximate the first side of the substrate. High-performance broadband photodetectors and other optoelectronics for converting light to electricity with enhanced absorption and carrier collection.

Abstract: Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.

Abstract: An image sensor includes: a pixel substrate that includes a plurality of pixels each having a photoelectric conversion unit that generates an electric charge through photoelectric conversion executed on light having entered therein and an output unit that generates a signal based upon the electric charge and outputs the signal; and an arithmetic operation substrate that is laminated on the pixel substrate and includes an operation unit that generates a corrected signal by using a reset signal generated after the electric charge in the output unit is reset and a photoelectric conversion signal generated based upon an electric charge generated in the photoelectric conversion unit and executes an arithmetic operation by using corrected signals each generated in correspondence to one of the pixels.

Abstract: Devices comprising a resistance-switching polymer film are described. Also described are methods of making the devices comprising the resistance-switching polymer film.

Abstract: A substrate has a front side including an electrical circuit and a rear side including an exposed zone that faces the electrical circuit. In an electrochemical treatment step, an electrical potential is laterally applied at least to the exposed zone of the rear side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes a lateral flow of electrical current at least in the exposed zone of the substrate. The lateral flow of current and the chemically reactive substance alter the substrate in at least the exposed zone.

Abstract: To provide a solid-state imaging element capable of further improving reliability. Provided is a solid-state imaging element including at least a first photoelectric conversion section, and a semiconductor substrate in which a second photoelectric conversion section is formed, in this order from a light incidence side, in which the first photoelectric conversion section includes at least a first electrode, a photoelectric conversion layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second electrode in this order, and a film density of the first oxide semiconductor layer is higher than a film density of the second oxide semiconductor layer.

Abstract: The present disclosure provides a display panel and a display device. A through-hole is defined in a bending area of the display panel, and after the bending area is bent along a bending center line, the through-hole forms a light transmitting area, and the light transmitting area is disposed on a light path of an electronic component. Based on the light transmitting area formed after bending the through-hole, the electronic component can be disposed under the display panel, thereby achieving a narrow frame design.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. A gate electrode metal layer is formed over the plurality of work function metal layers. The work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.

Abstract: Disclosed are a flexible display panel, a flexible display device and a deformation detection method thereof, used for detecting deformation of the flexible display panel. The flexible display panel provided by embodiments of the present disclosure includes a flexible substrate, a display device and a piezoelectric sensor arranged in a stacked mode. The piezoelectric sensor includes a first electrode, a second electrode, and a piezoelectric layer positioned between the first electrode and the second electrode; the piezoelectric sensor is configured to generate an electrical signal under the action of stress produced by bending the flexible display panel; and a signal processing chip in the flexible display device is configured to determine deformation parameters of the flexible display panel according to the electrical signal.

Abstract: The present disclosure relates to a neuron behavior-imitating electronic synapse device and a method of fabricating the same. According to one embodiment, the neuron behavior-imitating synapse device includes a first electrode having a lithium-doped surface, an active layer formed on the first electrode and including a polyelectrolyte and one or more metal nanoparticles, and a second electrode formed on the active layer.

Abstract: According to an embodiment, a method of manufacturing an organic electronic device including a stack including a first electrode layer, one or more functional layers, and a second electrode layer, the one or more functional layers and the second electrode layer being formed in this order on the first electrode layer, comprises: a first layer forming step of forming a first layer 24 among the layers included in the stack; and a second layer forming step of forming a second layer on the first layer by using a coating solution containing a material for the second layer and a solvent with boiling point of 160° C. or more, the second layer being in contact with the first layer. In the first layer forming step, the first layer is formed with a thickness t smaller than a desired thickness such that the first layer has the desired thickness T due to an increase in a thickness of the first layer as the second layer is formed.

Abstract: An element includes an electron transportation layer containing nanoparticles, a QD layer containing QD phosphor particles, and a mixed layer sandwiched between the electron transportation layer and the QD layer to be adjacent to these layers. The mixed layer contains QD phosphor particles and nanoparticles.