Patents Examined by Brian R. Peugh
  • Patent number: 11977548
    Abstract: A computing device is operable to receive a plurality of partition allocation requests based on execution of a corresponding plurality of query operations in conjunction with execution of a corresponding query. Processing a first partition allocation request of the plurality of partition allocation requests corresponding to execution of a first operation of the corresponding plurality of query operations is based on allocating a set of partitions of a plurality of partitions. Content is loaded into the set of partitions for access in executing the first operation. Access to the content via the set of partitions is facilitated in conjunction with execution of the first operation. The set of partitions are released based on determining the first operation has completed access of the content in conjunction with the execution of the first operation.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: May 7, 2024
    Assignee: Ocient Holdings LLC
    Inventor: George Kondiles
  • Patent number: 11960743
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: April 16, 2024
    Assignee: INNOVATIONS IN MEMORY LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 11954029
    Abstract: A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: April 9, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Paul Dennis Stultz, James T. Bodner, Kevin G. Depew
  • Patent number: 11941286
    Abstract: A storage device and methods of operation are disclosed. The device comprises a controller configured to execute a read command, a write command, a first vendor specific command, and a second vendor specific command, and further comprises a persistent memory and a non-persistent memory. When executing the first vendor specific command, the device begins operation in a first vendor specific mode. In this mode, the device stores write data in the non-persistent memory and does not immediately commit the write data to persistent memory. When executing the second vendor specific command, the device begins operation in a second vendor specific mode. In this mode, the device immediately commits write data to persistent memory. The first vendor specific mode is ideal when power supplies are healthy and redundant, while the second vendor specific mode is ideal when power supplies are not redundant and/or healthy.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Karimulla Sheik, Naga Shankar Vadalamani
  • Patent number: 11934700
    Abstract: Aspects of a storage device are provided that handle pairing and atomic processing of fused commands received from submission queues based on data structures such as a linked lists which the controller respectively associates with each submission queue. A memory of the storage device includes a plurality of data structures each associated with a different submission queue. A controller of the storage device receives a first command for a fused operation from a submission queue, stores the first command in a data structure, receives a second command for the fused operation from the submission queue, determines whether the second command corresponds to the fused operation, stores the second command in the data structure in response to the determination, and performs the fused operation in response to storing the second command. As a result, fused command handling may be achieved with minimal impact to queue arbitration logic and command latency.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rahul Jain, Arvind Kumar V M
  • Patent number: 11934661
    Abstract: Embodiments provide a method and computer program product including program instructions executable by a baseboard management controller in a multi-processor system to perform various operations. The operations include detecting a number of memory modules connected to each of a plurality of central processing units (CPUs) in the multi-processor system during boot, initiating operation of the multi-processor system as a single unified node in response to each of the CPUs being connected to an equal number of memory modules, and initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the CPUs each being connected to a first number of memory modules and a second set of one or more of the CPUs each being connected to a second number of memory modules that is different than the first number of memory modules.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: March 19, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Patent number: 11928359
    Abstract: A memory swapping method and apparatus are provided. The method includes: selecting n to-be-swapped-out pages; compressing the n to-be-swapped-out pages into n compressed blocks, and buffering the n compressed blocks in a compressed data buffer area; organizing at least one of the n compressed blocks into m to-be-written units; and writing the m to-be-written units into a swap area of a non-volatile storage device in a maximum of m batches, where at least one of the m to-be-written units is stored in a segment of continuous space in the swap area. The method reduces a quantity of write times during memory swapping, thereby prolonging a service life of the non-volatile storage device.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: March 12, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chengke Wang, Yongjun Wei, Xie Miao, Wei Fang
  • Patent number: 11922052
    Abstract: A method including generating a new storage object derived from an existing storage object, wherein the new storage object has a first historical record identifying previous actions taken to generate the existing storage object. The method further includes generating a second historical record for the new storage object, wherein the second historical record represents the first historical record and an action that generated the new storage object from the existing storage object.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: March 5, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Sillifant, Taher Vohra, Robert Lee, Michael Richardson
  • Patent number: 11921646
    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes memory for storage of data, an IOMMU coupled to the memory, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the memory, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the memory pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: David Koufaty, Rajesh Sankaran, Anna Trikalinou, Rupin Vakharwala
  • Patent number: 11922054
    Abstract: Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Olivier Duval, Christopher Joseph Bueb
  • Patent number: 11922042
    Abstract: A method is described.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Scality, S.A.
    Inventors: Lam Pham Sy, Frederic Ferrandis, Benoit Artuso
  • Patent number: 11914515
    Abstract: A cache memory device is provided in the disclosure. The cache memory device includes a first AGC, a compression circuit, a second AGC, a virtual tag array, and a comparator circuit. The first AGC generates a virtual address based on a load instruction. The compression circuit obtains the higher part of the virtual address and generates a target hash value based on the higher part of the virtual address. The second AGC generates the lower part of the virtual address based on the load instruction. The virtual tag array obtains the lower part and selects a set of memory units. The comparator circuit compares the target hash value to a hash value stored in each memory unit of the set of memory units. When the comparator circuit generates the virtual tag miss signal, the comparator circuit transmits the virtual tag miss signal to the reservation station.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: February 27, 2024
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Junjie Zhang, Mengchen Yang, Jing Qiao, Jianbin Wang
  • Patent number: 11907531
    Abstract: Some techniques described herein relate to determining how to optimally store datasets in a multi-tiered storage device with compression. In one example, a method includes assigning, to a data partition of a dataset, a priority based on access patterns of the data partition. Compression data is accessed describing results of compressing a data sample associated with the data partition using multiple compression schemes. Based both on the priority of the data partition and the compression data, a storage tier is determined for storing the data partition in the multi-tiered storage device. Further, based both on the priority of the data partition and the compression data, a compression scheme is determined for compressing the data partition for storage in the multi-tiered storage device. The data partition is compressed using the compression scheme to produce a compressed data partition, and the compressed data partition is stored in the storage tier.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 20, 2024
    Assignee: Adobe Inc.
    Inventors: Raunak Shah, Koyel Mukherjee, Khushi, Kavya Barnwal, Karanpreet Singh, Harsh Kesarwani, Ayush Chauhan
  • Patent number: 11901899
    Abstract: A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2n?1 times.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: February 13, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Chi-Shun Lin
  • Patent number: 11893252
    Abstract: Processing can be performed to persistently record, in a log, a write I/O that writes first data to a target logical address. The processing can include: allocating storage for a first page buffer (PB) located at offsets in a PB pool of non-volatile storage of the log; enqueuing a request to an aggregation queue to persistently store the first data to the first PB of the log, wherein the request identifies the offsets of the PB pool of non-volatile storage which correspond to the first PB; and integrating the request into the aggregation queue. Integrating can include: determining whether a contiguous segment of the offsets of the request is adjacent to a second contiguous segment of the aggregation queue; and responsive to determining the contiguous segment is adjacent to the second contiguous segment, merging the first and second contiguous segments and generating an aggregated continuous segment.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: February 6, 2024
    Assignee: Dell Products L.P.
    Inventors: Svetlana Kronrod, Vladimir Shveidel, David Bernard, Vamsi K. Vankamamidi
  • Patent number: 11880305
    Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: January 23, 2024
    Assignee: FLC Technology Group, Inc.
    Inventor: Sehat Sutardja
  • Patent number: 11880281
    Abstract: Embodiments are described for a system that automatically determines the ideal backup target for the backup agent to send its backup data. The system will automatically create and destroy temporary backup targets in order to handle the current backup traffic and provide the optimal throughput based on speed of the backup agent and reliability of the storage target. The backup agent is able to send incremental backups to any temporary backup target, which are later consolidated on the storage target after the agent has disconnected from the system. The final storage target may be an original primary storage target for the data asset or one of the temporary storage targets.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: January 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Mark Malamut, Jennifer M. Minarik, Brian E. Freeman
  • Patent number: 11880567
    Abstract: A request to perform a storage operation for a storage system is received. It is determined that the requested storage operation is associated with a policy that requires a quorum of approvals before being allowed to be performed. It is determined whether the quorum of approvals has been obtained. In response to a determination that the quorum of approvals has been obtained, a command to perform the requested operation is provided to the storage system.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 23, 2024
    Assignee: Cohesity, Inc.
    Inventors: Harsha Vardhan Jagannati, Abhishek Sharma
  • Patent number: 11868309
    Abstract: A priority queue including an order of local data relocation operations to be performed by a plurality of solid-state storage devices is maintained. An indication of a new local data relocation operation is received from a solid-state storage device of the plurality of solid-state storage devices for data stored at the solid-state storage device, the indication including information associated with the data. The new local data relocation operation is inserted into a position in the order of the priority queue based on the information associated with the data.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 9, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Sankara Vaideeswaran, Hari Kannan, Gordon James Coleman
  • Patent number: 11868656
    Abstract: A method for managing data storage using a distributed file system. A file system volume associated with a write request received at a data management subsystem is identified. A logical block device associated with the file system volume is identified. A plurality of data blocks is formed based on the write request. The plurality of data blocks is distributed across a plurality of node block stores in a distributed block layer of a storage management subsystem of the distributed file system. Each of the plurality of node block stores corresponds to a different node of a plurality of nodes in the distributed storage system. The storage management subsystem operates separately from but in communication with the data management subsystem.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 9, 2024
    Assignee: NetApp, Inc.
    Inventors: Ravikanth Dronamraju, Arindam Banerjee