Abstract: Systems and method for power control for a decoder are disclosed. In one aspect, a decoder for a communication bus is put into a sleep or low power mode when the bus is idle such as when blanking information is sent over a camera serial interface (CSI) bus. By alerting the decoder that there is an opportunity for low power operation, power consumption may be reduced and, particularly for battery operated mobile devices, a time to recharge metric may be improved, which improves the user experience.

Abstract: An information processing device includes processing circuitry configured to determine whether or not there is integrity in predetermined data regarding a boot sequence of an Operating System (OS) during execution of shutdown of the OS, arid suspend shutdown of the OS when it is determined that there is no integrity in the predetermined data.

Abstract: A system and method for connecting a processing device to a functional device connected to or in a base unit of a communications network, the base unit having a transmitter and the processing device having a memory, a display and an operating system. A first peripheral device is adapted to be coupled to the processing device via a generic communications protocol, the first peripheral device having a receiver and at least one fixed or configurable endpoint of the functional device exposed on the first peripheral device. The base unit and the first peripheral device is adapted to transmit and receive data respectively over the communications network from the functional device to the processing device via the at least one fixed or configurable endpoint using the generic communications protocol for communication between the processing device and the first peripheral device.

Abstract: A system and method for connecting a processing device to a functional device connected to or in a base unit of a communications network, the base unit having a transmitter and the processing device having a memory, a display and an operating system. A first peripheral device is adapted to be coupled to the processing device via a generic communications protocol, the first peripheral device having a receiver and at least one fixed or configurable endpoint of the functional device exposed on the first peripheral device. The base unit and the first peripheral device is adapted to transmit and receive data respectively over the communications network from the functional device to the processing device via the at least one fixed or configurable endpoint using the generic communications protocol for communication between the processing device and the first peripheral device.

Abstract: A telecommunications apparatus including a lighting apparatus, the lighting apparatus having: a plurality of light sources, an illumination state of the light sources being controllable according to control signals; circuitry connected to the plurality of light sources, wherein the circuity is configured to provide control signals to the light sources; and a plug connected to the circuitry, wherein the plug is configured to connect to an external port of a first telecommunications device, and configured as an interface for control signals from the first telecommunications device to the circuitry. The plurality of light sources are arranged such that a change in illumination state of the plurality of light sources provides a visual indication on a subject telecommunications device.

Abstract: A processor includes at least one socket and at least one memory. Each socket includes a first die and a second die. The first die receives a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputs a boot-completion signal after completing the boot procedure. The second die receives the internal boot-enable signal and the boot-completion signal from the first die to execute the boot procedure. The second die is electrically connected to the first die through a communication bus. The memory is electrically connected to the second die. When the first die executes the boot procedure, the first die accesses the memory through the communication bus and the second die.

Abstract: An autonomous driving controller includes a plurality of parallel processors operating on common input data. Each of the plurality of parallel processors includes a general processor, a security processor subsystem (SCS), and a safety subsystem (SMS). The general processors, the SCSs, and the SMSs of the plurality of parallel processors are configured to first, boot the plurality of SCSs from ROM second, boot the plurality of SMSs of the plurality of parallel processors from RAM or ROM, and, third, boot the plurality of general processors of the plurality of parallel processors from RAM. Between booting of the SCSs and the SMSs, at least one of the plurality of SCSs may load SMS boot code into the RAM that is dedicated to the plurality of SMSs.

Abstract: Disclosed are a method and a Universal Flash Storage (UFS) system for performing save state switching using selective lanes between a first electronic device and a second electronic device. The method includes: determining, by the first electronic device, whether a data request is received from an application layer of the first electronic device; and performing, by the first electronic device, at least one of: setting a first lane from among a plurality of lanes between the first electronic device and the second electronic device to an active state and the other lanes from among the plurality of lanes to a power save state based on determining that the data request is not received from the application layer of the first electronic device; and setting the plurality of lanes between the first electronic device and the second electronic device to the active state based on determining that the data request is received from the application layer of the first electronic device.

Abstract: A method includes determining, by one or more processing entities associated with at least one of: one or more low voltage drive circuits (LVDCs) and one or more other LVDCs, an initial data conveyance scheme and an initial communication scheme for each communication of a plurality of communications on one or more lines of a bus. The method further includes determining a desired number of channels for each communication of the plurality of communications based on the initial data conveyance scheme and the initial communication scheme, a desired total number of channels for the plurality of communications based on the desired number of channels, determining whether the desired total number of channels for the plurality of communications exceeds a total number of available channels. If not, allocating the desired number of channels to each communication of the plurality of communications in accordance with the channel allocation mapping.

Abstract: An ergonomic power supply for a computer system includes a printed circuit board assembly configured to convert a mains electricity input to voltage-regulated, direct-current (DC) outputs. The printed circuit board assembly defines a mains input and has one or more DC output connectors. An enclosure houses a fan and the printed circuit board assembly. The enclosure has a rear panel, a front panel positioned opposite the rear panel relative to the printed circuit board assembly. A side panel is positioned between the front and rear panel. The mains connector extends through an aperture defined by the rear panel of the enclosure. The one or more DC output connectors extend through the side panel. Such an arrangement provides significantly easier access to the power supply outputs compared to conventional power supplies. Associated computer systems also are described.

Abstract: A system and method for connecting a processing device to a functional device connected to or in a base unit of a communications network, the base unit having a transmitter and the processing device having a memory, a display and an operating system. A first peripheral device is adapted to be coupled to the processing device via a generic communications protocol, the first peripheral device having a receiver and at least one fixed or configurable endpoint of the functional device exposed on the first peripheral device. The base unit and the first peripheral device is adapted to transmit and receive data respectively over the communications network from the functional device to the processing device via the at least one fixed or configurable endpoint using the generic communications protocol for communication between the processing device and the first peripheral device.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

Abstract: A receptacle includes a plurality of universal serial bus (USB) ports including a USB Type C PD port and a USB Type C port couplable to respective devices for charging, a controller coupled to the USB ports and including a dynamic power sharing logic, the controller structured to: determine whether one or more USB ports are coupled to the respective devices and manage first power negotiation and dynamic power sharing if both USB ports are coupled to respective devices or manage second power negotiation if only one USB port is coupled to respective device; an AC/DC converter including a gallium nitride (GaN) MOSFET on at least one of the primary side or the secondary side of the AC/DC converter, the AC/DC converter structured to provide high power to the USB Type C PD port; and a DC/DC converter structured to provide low power to the USB Type C port.

Abstract: A method includes obtaining, by a first processing entity, first data communication capabilities of a first host device. The first host device and the first processing entity are associated with a first low voltage drive circuit. The method further includes obtaining, by a second processing entity, second data communication capabilities of a second host device. The second host device and the second processing entity are associated with a second low voltage drive circuit. The method further includes reconciling, by one or more of the first and second processing entities, the first and second data communication capabilities to produce reconciled data communication capabilities and determining a data conveyance scheme and a data communication scheme for a one-to-one communication between the first and second low voltage drive circuits based on the reconciled data communication capabilities.

Abstract: Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.

Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Abstract: A data forwarding chip and a server are disclosed. The server includes a data forwarding chip, a network interface card, and a processor. The data forwarding chip is separately connected to the network interface card and the processor through a bus. After receiving a data forwarding request sent by the processor or the network interface card, the data forwarding chip forwards, based on a destination address of the data forwarding request through an endpoint port that is on the forwarding chip and that is directly connected to a memory space corresponding to the destination address of the data forwarding request, to-be-forwarded data specified in the data forwarding request, such that when the server sends or receives data, cross-chip transmission of data between processors occurs, thereby reducing a data transmission delay.

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.