Abstract: A system, method, and computer-readable medium are disclosed for securing hot-pluggable ports, such as USB ports, of an information handling system, by isolating a dedicated controller from the operating system of the information handling system. Devices that are to be allowed to be enabled at the ports are determined. A hash signature is created and saved to verify the devices. The controller and ports are held in reset until the devices are authenticated.

Abstract: An electronic device includes a transmit buffer, a receive buffer, a communication port, and a controller. The controller is to: communicate with a target device via a data link established via the communication port; determine a throughput ratio between the transmit buffer and the receive buffer; in response to a determination that the throughput ratio is above a threshold, transmit a request to the target device to change an aspect of the data link, where the request includes a payload size indicating an amount of data to be transmitted from the electronic device to the target device; and in response to receiving a grant message associated with the request, increase an amount of transmit lanes within the data link from the electronic device to the target device.

Abstract: An information handling system includes a compression client, a memory, and a SDXI hardware module. The compression client issues a compression request for a block of data that is uncompressed. The memory has multiple storage locations identified by addresses, which include a source address and a destination address. The SDXI hardware module performs compression of the block of data to create compressed data of the block of data. The SDXI hardware module determines whether an amount of the compression of the block of data is less than a threshold amount of compression. In response to the amount of the compression being less than the threshold amount of compression, the SDXI hardware module disregards the compressed data of the block of data, and utilizes the uncompressed block of data in a source address. The SDXI hardware module updates metadata for the block of data to indicate that data returned to compression client is uncompressed.

Abstract: Techniques are disclosed relating to a method that includes monitoring, by a sideband processor, a plurality of operating conditions of a computer system using a first set of commands. This first set of commands are sent utilizing a particular command protocol over a particular communication bus. In addition, the sideband processor may be modified to support a second set of commands. The sideband processor may receive data for a particular device in the computer system. The sideband processor may modify a first command of the first set of commands to include a second command of the second set of commands. This second command may include an address associated with the particular device and at least a portion of the data. The sideband processor may then send the modified first command to a controller hub using the particular command protocol over the particular communication bus.

Abstract: Example of systems with rotatable port units are described. In an example, a system includes a control unit, a first port unit with a first set of ports coupled to the control unit, and a second port unit with a second set of ports coupled to the control unit. The second port unit is mounted on the first port unit and is rotatable with respect to the first port unit. The control unit is to enable a sub-set of ports from the second set of ports and the first set of ports based on a rotational position of the second port unit with respect to the first port unit.

Abstract: An electronic device may include a connection unit including four ports for connecting an external audio device; a codec configured to generate an audio signal transmitted to the external audio device; a first switch unit configured to, if the external audio device is electrically connected to the electronic device, connect the first port and the second port with the codec; a second switch unit configured to, if the external audio device is electrically connected to the electronic device, connect the third port and the fourth port with the codec; a third switch unit configured to swap connection directions of the third port and the fourth port according to a coupling orientation of the external audio device and the electronic device; and a ground unit connected to the third port and the fourth port and configured to ground one of the third port and the fourth port.

Abstract: A centralized access control circuit includes a memory, a sub-circuit, and a memory controller. The memory includes a plurality of lock bits mapped to a plurality of bytes of a peripheral register included in a peripheral. The sub-circuit receives, from a processor core, an access request to access a set of bytes of the plurality of bytes. The sub-circuit grants a first level of access privilege to the processor core based on an identifier of the processor core and an address of the set of bytes included in the access request. The memory controller receives the access request and grants, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core. The processor core accesses the set of bytes based on the first and second levels of access privileges.

Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.

Abstract: Method for controlling commands suitable to be processed by a peripheral (2) comprising the following steps implemented by a control circuit (6) connected to a communication bus (8), a command circuit (4) and the peripheral (3) also being connected to the communication bus (8): granting or refusing authorization to the command circuit (4) to transmit a command signal of the peripheral via the bus (8), detecting the possible transmission of the command signal for the peripheral by the command circuit via the bus (8), implementing protection measures (614) when the control circuit detects that the command signal has been transmitted as the control circuit has not granted authorization, or that the command signal has not been transmitted as the control circuit has granted authorization.

Abstract: A method may include initializing operation of a baseboard management controller at an information handling system. The baseboard management controller includes a real time clock. The method further includes receiving clock information from a real time clock circuit included at a field programmable gate array. The clock information at the real time clock at the baseboard management controller can be updated with the clock information received from the real time clock circuit included at the field programmable gate array.

Abstract: A system, computer-readable media and computer-implemented method for automated network adapter activation in connection with fibre channel uplink mapping. The system includes a non-virtualized storage area network switch having a plurality of fibre channel ports. Each of the fibre channel ports is coupled to a corresponding cable to at least partly define a fibre channel uplink. The system also includes a plurality of client devices. Each client device has a network adapter.

Abstract: A low voltage drive circuit includes a transmit digital to analog circuit (DAC), a receive analog DAC and a drive sense circuit configured to receive transmit digital data. The transmit DAC is configured to convert transmit digital data into an analog outbound data signal and the receive analog DAC is configured to convert an analog outbound data signal into an analog transmit signal. The drive sense circuit is configured to drive the analog transmit signal on to a bus coupled to the low voltage drive circuit as a signal that varies loading on the bus at a first frequency to represent the analog outbound data signal. The drive sense circuit is further configured to receive an analog receive signal from the bus at a second frequency, convert the analog receive signal into an analog inbound data signal, convert the analog inbound data signal into received digital data, and output the received digital data.

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.

Abstract: A method of transferring data from a first bus to a second bus across an asynchronous interface using an asynchronous bridge. The bridge comprises a bus slave module, connected to the first bus, comprising a forward-channel initiator in a first power and/or clock domain; and a bus master module, connected to the second bus, comprising a forward-channel terminator in a second power and/or clock domain. The forward-channel initiator and terminator are in communication to form a forward lockable mutex for arbitrating access to signals used to transfer data from the first domain to the second domain. If the mutex is locked, a forward data channel is used to transfer data between the domains. Otherwise if the mutex is unlocked, the forward channel initiator toggles a status request signal and the forward channel terminator toggles a status acknowledge signal in response, the mutex thereby becoming locked.

Abstract: A system for automatically addressing serially connected slave devices includes a master device and multiple slave devices each including a serial communication transceiver, an address input port, an address output port, and a controller. The system also includes a serial communication wiring bus connected between the serial communication transceivers of the master and slave devices, and at least one digital address line connected between the address input ports and the address output ports. Each controller is configured to receive a PWM or PFM signal from a previous one of the multiple slave devices, determine an address for the slave device including the controller according to the received PWM or PFM signal, and transmit a PWM or PFM signal indicative of the determined address to a subsequent one of the multiple slave devices.

Abstract: The signal collection method is a method that collects internal states indicated by signals in an electronic circuit device including a bus, the signal collection method including: storing the internal states with a fine resolution data storage by obtaining the internal states per a first period; per a second period, which is longer than the first period: obtaining a first data transfer amount, which is a data amount transferred by the bus, via a coarse resolution data storage; calculating a difference between a second data transfer amount and the first data transfer amount obtained in the obtaining, the second data transfer amount being calculated in advance and obtained from a cycle pattern generator; and determining whether the difference calculated in the calculating is within a predetermined range to stop storing in the storing when it is determined that the difference is not within the predetermined range.

Abstract: A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

Abstract: A bi-directional signal transmission connection cable is disclosed. The bi-directional signal transmission connection cable can be connected between a first and a second electronic device. The bi-directional signal transmission connection cable includes a first connection port, a second connection port, a first repeater chip, a second repeater chip and a plurality of transmission wires. The first and the second repeater chips are symmetrically disposed in the first and the second connection ports. The first repeater chip has a first set of adjustment parameters, and the second repeater chip has a second set of adjustment parameters. Thus, when a signal is transmitted between the first and the second electronic devices via the first connection port, the second connection port, and the plurality of transmission wires, the signal is adjusted by the first set of adjustment parameters and the second set of adjustment parameters.

Abstract: A method for executing device management commands includes providing a device management command queue indication. The method also includes receiving, from a host in response to providing the device management command queue indication, device management commands and a respective command type for each device management command. The method also includes determining a command execution order for the device management commands based on the command types corresponding to respective device management commands and queueing, in a device management command queue, the device management commands based on the command execution order. The method also includes executing the device management commands according to the device management command queue. The method also includes communicating, to the host, a command execution indication responsive to executing the device management commands.

Abstract: A chip processing device and a method for chip processing using the same is provided, where the device can program, detect, reset or inspect a plurality of chips, and meanwhile has one or more functions of programming, detecting, identifying, resetting or inspecting. The plurality of chips has different communication interfaces, and/or uses different communication protocols. The chip processing device can be configured to program, detect, identify, reset or inspect a chip after obtaining the model of the chip to be processed, thus having higher universality.