Abstract: A method includes obtaining, by a first processing entity, first data communication capabilities of a first host device. The first host device and the first processing entity are associated with a first low voltage drive circuit. The method further includes obtaining, by a second processing entity, second data communication capabilities of a second host device. The second host device and the second processing entity are associated with a second low voltage drive circuit. The method further includes reconciling, by one or more of the first and second processing entities, the first and second data communication capabilities to produce reconciled data communication capabilities and determining a data conveyance scheme and a data communication scheme for a one-to-one communication between the first and second low voltage drive circuits based on the reconciled data communication capabilities.

Abstract: Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.

Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Abstract: A data forwarding chip and a server are disclosed. The server includes a data forwarding chip, a network interface card, and a processor. The data forwarding chip is separately connected to the network interface card and the processor through a bus. After receiving a data forwarding request sent by the processor or the network interface card, the data forwarding chip forwards, based on a destination address of the data forwarding request through an endpoint port that is on the forwarding chip and that is directly connected to a memory space corresponding to the destination address of the data forwarding request, to-be-forwarded data specified in the data forwarding request, such that when the server sends or receives data, cross-chip transmission of data between processors occurs, thereby reducing a data transmission delay.

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Abstract: A semiconductor device is configured so that two or more master devices access a slave device via a bus. The semiconductor device includes: a priority generation circuit that generates a priority based on a transfer amount between a specific master device and a specific slave device; and an arbitration circuit that performs an arbitration based on the priority when competition of the accesses occurs.

Abstract: A system for automatically addressing serially connected slave devices includes a master device and multiple slave devices each including a serial communication transceiver, an address input port, an address output port, and a controller. The system also includes a serial communication wiring bus connected between the serial communication transceivers of the master and slave devices, and at least one digital address line connected between the address input ports and the address output ports. Each controller is configured to receive a PWM or PFM signal from a previous one of the multiple slave devices, determine an address for the slave device including the controller according to the received PWM or PFM signal, and transmit a PWM or PFM signal indicative of the determined address to a subsequent one of the multiple slave devices.

Abstract: Disclosed by the present application are a method, master device and system for data communication. The method comprises: initiating a communication signal to an interface in an interface module; when response information from a slave device connected in the interface is received, adding physical ID information of the interface into an online queue, wherein the probability that interfaces in the online queue is subsequently initiated by the communication signal is higher than that of interfaces in an idle queue; and receiving data information transmitted by the slave device in the interface. The data communication master device of the present application comprises a communication signal initiation unit, an online interface identification unit and a data information receiving unit corresponding to the implementation of steps of the described method. Therefore, the communication network for multiple slave devices and a master device has high communication efficiency.

Abstract: A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.

Abstract: Reconfigurable interconnection nodes and interface modules are provided. The reconfigurable interconnection node includes a circuit board with a processing unit executing instructions stored on memory to provide operating system software, at least one bus, and at least one bus connector. The reprogrammable interconnection node also includes at least one system interface module operably connected to the circuit board via the at least one bus, wherein the system interface module is configured to communicate with or exchange data with at least a first external system.

Abstract: Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

Abstract: A structure is provided for a structure for providing electrical connections across a connection interface is provided. The structure may include one or more signal connections, a plurality of reference connections, and one or more high-pass filters. One or more of the reference connections is configured to connect a first reference voltage in a first region on a first side of the interface with a second reference voltage in a second region on a second side of the interface. One or more of the reference connections in a first class of reference connections is coupled one or more of the reference voltages through the one or more high-pass filters, and low-bandwidth information is communicated across the one or more reference connections in the first class of reference connection.

Abstract: Provided are a method and an apparatus for controlling power consumption, a board, an electronic device and a storage medium. The method is applied to a board, and the board includes a dynamic random memory. The method includes: obtaining a data flow of the board; and controlling an active bandwidth of the dynamic random memory according to the data flow.

Abstract: A single-level single-line full-duplex bus communication method and system are disclosed. The method includes: transmitting, by a first signal transceiver, data according to a first internal transmitter clock F1, simultaneously monitoring a level change on a bus, and parsing received data; transmitting, by a second signal transceiver, data according to a second internal transmitter clock F2, simultaneously monitoring the level change on the bus, and parsing received data; and communicating between the first and second signal transceivers by means of a single line, wherein the first and second transmitter clocks satisfy a relationship: F1>F2*(length of data unit+2). The system achieves single-level single-line full-duplex communication by using different coding formats and different internal transmitter clocks, whereby the number of signal lines can be reduced, single-level communication can be achieved by using universal digital levels, i.e., 0, 1, and the hardware implementation difficulty can be reduced.

Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.

Abstract: An indication that a virtual machine is starting is received. Requested data blocks associated with the virtual machine are identified. Based on identifiers of the requested data blocks, a trained learning model is used to predict one or more subsequent data blocks likely to be requested while the virtual machine is starting. The one or more subsequent data blocks are caused to be preloaded in a cache storage.

Abstract: Control device for a power over Ethernet system having multiple power source devices comprises plural control circuits and a signal bus connecting them. Each control device connects plural power source devices and plural port switches, which controls power supply to a port to be connected by a power consuming device. Detection circuit detects at least one power supply state combination. Control signal generator picks up a power control combination signal corresponding to a detected power supply state combination from a power supply to power control look-up-table, upon change in the power supply state and provides the power control signals to corresponding port switches.

Abstract: Disclosed are a module assembly and a multi-master communication method thereof, and more particularly, a module assembly including a plurality of modules capable of transmitting/receiving data by forming an open drain based one-wire communication bus upon mutual combination, in which at least one module requiring the data transmission among the plurality of modules performs first declaration for a transmission intention by outputting a low signal within a predetermined first arbitration time when at least one module is in an on state by sensing the one-wire communication bus state, at least one module performing the first declaration for the transmission intention performs second declaration for the transmission intention by outputting a high signal within a second arbitration time, and a module which outputs the high signal last within the second arbitration time secures final bus occupation.

Abstract: A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.