Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.

Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

Abstract: A method, non-transitory computer readable medium, and storage server device that determines with a service processor when a system processor has experienced an error, the system processor coupled to a data storage device via a system port of the data storage device. Diagnostic information is retrieved with the service processor from the data storage device via a service port of the data storage device, when the system processor is determined to have experienced an error. The diagnostic information includes error or exception information associated with one or more hardware components. The retrieved diagnostic information is output by the service processor.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for modifying symbols in a data set prior to re-processing.

Abstract: The semiconductor device includes a latch pulse generator and a data latch unit. The latch pulse generator generates a test section signal in response to a test pulse signal. Further, the latch pulse generator generates a first latch pulse signal in response to the test pulse signal and the test section signal. The data latch unit latches a selection data in response to the first latch pulse signal to generate a fuse data for programming a fuse array.

Abstract: A machine for evaluating failing software programs, a non-transitory computer-readable storage medium with an error analysis program stored thereon and an error analysis program executed by a microprocessor are disclosed. In one embodiment a machine for investigating an error source in a software program includes a microprocessor coupled to a memory, wherein the microprocessor is programmed to determine whether a failure of an error-prone program step occurs reproducibly by providing the software program with the error-prone program step, executing program steps preceding the error-prone program step, executing the error-prone program step a number of times and calculating a failure probability for the error-prone program step.

Abstract: A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.

Abstract: Aspects of a method and system for hybrid redundancy for electronic networks are provided. A first line card may comprise a first instance of a network layer circuit, a first instance of a physical layer circuit, and an interface to a data bus (e.g., an Ethernet bus) for communicating with a second line card. In response to detecting a failure of the first instance of the network layer circuit, the first instance of the physical layer circuit may switch from processing of a signal received via the first instance of the network layer circuit to processing of a signal received via the interface. The system may comprise a second line card. The second line card may comprise a second instance of the network layer circuit. The second instance of the network layer circuit may be coupled to the data bus.

Abstract: A method, computer program product, and computing system for defining a transactional log file for a data storage system including defining a transactional log file for a data storage system including a data array. A plurality of IO requests for the data storage system are processed. The transactional log file is updated to include information concerning the plurality of IO requests, wherein the information includes an LGT indicator for each of the plurality of IO requests. The occurrence of a malfunction within the data storage system is sensed.

Abstract: The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines.

Abstract: A device includes a first processing unit and a second processing unit. The first processing unit is configured to execute a performance test on the device. The second processing unit is in communication with the first processing unit, and is configured to migrate an application from the second processing unit to the first processing unit. The second processing unit is further configured to detect a failure of the first processing unit, to migrate the application to a third processing unit in response to the failure of the first processing unit, and to assign a first plurality of ports to the third processing unit in response to the failure of the first processing unit.

Abstract: A network-based storage system includes multiple storage devices and system controllers. Each storage device in multiple aggregates of storage devices can include ownership portion(s) that are configured to indicate a system controller to which it belongs. First and second system controllers can form an HA pair, and can be in communication with each other, the storage devices, and a separate host server. A first system controller controls an aggregate of storage devices and can facilitate an automated hotswap replacement of a second system controller that controls another aggregate of storage devices with a separate third system controller that subsequently controls the other aggregate of storage devices.

Abstract: Providing admission control for a request may comprise creating a process flow associated with the request, the process flow identifying a plurality of computer-implemented components and a flow of transactions occurring between the computer-implemented components; executing the flow of transactions on the plurality of computer-implemented components; logging the flow of transactions; monitoring the flow of transactions to detect a problem in the flow or one or more of the components, or combination thereof; responsive to not detecting a problem in the flow or one or more of the components, or combination thereof, allowing the request to proceed; and responsive to detecting a problem in the flow or one or more of the components, or combination thereof, not allowing the request to proceed.

Abstract: An “erasure code” is an encoding of multiple different sets of data. Redundant copies of data are maintained in such erasure codes, thereby utilizing only a fraction of the storage capacity of unencoded copies. Erasure codes are efficiently generated, with a minimum of processing resources utilizing XOR functionality. Additionally, erasure codes are generated from local data, thereby avoiding the consumption of network resources. At least one unencoded copy of a set of data is maintained, while the remaining, redundant copies are encoded into erasure codes. Requests for data are provided from the unencoded copy. Should it fail, a new unencoded copy can be generated by another computing device having access to both an erasure code as well as unencoded copies of the other data that was also pressed into that erasure code. Multiple failures can be survived through recursive application of such a decoding of encoded data.

Abstract: An automatic technique for a timely diagnostic uses a cloud service and includes (1) after a memory dump file is generated, uploading the dump file and system configurations to an analysis server, (2) extracting key call stacks from the dump file in the server, (3) searching a cloud-based knowledge base for entries corresponding to contents of the call stack and the system configurations (like model, SW version, etc.), these entries representing known issues having similar call stack contents and/or system configurations. If relevant knowledge base entries are found, then they are used to identify a root cause and suggest solutions. If no relevant knowledge base entries are found, this result is reported along with any other potentially useful data from the dump file analysis, such as an identification of a product area for a program identified by the dump file name.

Abstract: Provided are a system, computer program, and method for restoring redundancy in a storage group when a storage device in the storage group fails. In response to detecting a failure of a first storage device in a storage group, wherein the storage group stores each of a plurality of extents in the first storage device and a second storage device to provide redundancy, a determination is made whether a spare storage device that has a storage capacity less than that of the storage group. One of the extents in a storage location in the second storage device that is beyond an upper limit of positions in the spare storage device is moved to a new storage location. The spare drive is incorporated into the storage group to provide redundant storage for the storage group, wherein the extents in the storage group are copied to the spare drive.

Abstract: Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Abstract: A processing-based bypass “fail open” mode is provided for an intrusion prevention system by a primary process running on a first logical core (lcore) is used as a control plane, which invokes bypass-open run-to-completion threads in other lcores comprising a bypass data plane, and which spawns a secondary process to fully configure intrusion prevention threads on other lcores to create an Intrusion Prevention System data plane. Upon a ready signal from the secondary process, the primary process quiesces such that the secondary process IPS data plane exclusively owns and executes on the other lcores.

Abstract: Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Abstract: An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set.