Abstract: An information processing device includes: a memory configured to hold values of state variables included in an evaluation function presenting energy and a weight value for each set of the state variables; and a processor coupled to the memory and configured to: calculate an energy change value when each of the values of the state variables is set as a next change candidate based on the values of the state variables and the weight value; calculate a total energy change value by adding a penalty value according to an excess amount violating an inequality constraint, to each of the energy change values calculated for the state variables, the excess amount being calculated based on a coupling coefficient and a threshold value; and change any value of the state variables in the memory based on a set temperature value, a random number value, and the total energy change values.

Abstract: Apparatus and associated methods relate to providing a modified CORDIC approach and implementing the modified CORDIC approach in SoftMax calculation to reduce usage of hardware resources.

Abstract: A hardware module comprising circuitry configured to: store a sequence of n bits in a register of the hardware module; generate a signed integer comprising a magnitude component and a sign bit by: if the most significant bit of the sequence of n bits is equal to one: set each of the n?1 of the most significant bits of the magnitude component to be equal to the corresponding bit of the n?1 least significant bits of the sequence of n bits; and set the sign bit to be zero; if the most significant bit of the sequence of n bits is equal to zero: set each of the n?1 of the most significant bits of the magnitude component to be equal to the inverse of the corresponding bit of the n?1 least significant bits of the sequence of n bits; and set the sign bit to be one.

Abstract: Systems, apparatuses, and methods related to a memory array data structure for posit operations are described. Universal number (unum) bit strings, such as posit bit string operands and posit bit strings representing results of arithmetic and/or logical operations performed using the posit bit string operands may be stored in a memory array. Circuitry deployed in a memory device may access the memory array to retrieve the unum bit string operands and/or the results of the arithmetic and/or logical operations performed using the unum bit string operands from the memory array. For instance, an arithmetic operation and/or a logical operation may be performed using a first unum bit string stored in the memory array and a second unum bit string stored in the memory array. The result of the arithmetic operation and/or the logical operation may be stored in the memory array and subsequently retrieved.

Abstract: Embodiments relate to a system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using a systolic array comprising hardware for solving the particular type of the differential equation. The systolic array processes each node to generate a node for a subsequent time-step using a sub-array comprising a plurality of branches, each branch comprising a respective set of arithmetic units arranged in accordance with a corresponding term of the discretized form of the differential equation, and an aggregator configured to aggregate the corresponding terms from each branch to generate node data for the subsequent time-step.

Abstract: The analog multiplier includes a first signal input module, and a second signal input module or a third signal input module. The first signal input module is configured to output a frequency modulation signal. The second signal input module includes a first energy storage unit, a first switch unit, and a second switch unit. The first switch unit and the second switch unit are alternately turned on or turned off based on a frequency of the frequency modulation signal. The third signal input module includes a second energy storage unit, two third switch units, and two fourth switch units. The third switch unit and the fourth switch unit are alternately turned on or turned off based on the frequency of the frequency modulation signal.

Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.

Abstract: A device includes a matrix transpose component, a matrix processing component, a data alignment component, and a data reduction component. The matrix transpose component is configured to transpose an input matrix of elements to output an output matrix of the elements that have been transposed. The matrix processing component is configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix. The data alignment component is configured to modify at least a portion of elements of a result of the matrix processing component. The data reduction component is configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values.

Abstract: A random number generating device includes a particle detector, a pulse generator, a clock counter, and a random number converter. The particle detector detects particles emitted from a radioactive isotope. The pulse generator generates pulses corresponding to the particles. The clock counter counts the number of clock cycles during time intervals between the pulses and generates a plurality of count values. The random number converter adjusts a clock frequency, based on a minimum value and a maximum value of the plurality of count values and converts a target count value generated depending on the adjusted clock frequency into a random number.

Abstract: The exemplary embodiments of the present invention provide a quantum random number generation apparatus according to an exemplary embodiment of the present invention including: a space-division semiconductor detector including a plurality of cells, each individually absorbing a plurality of emission particles emitted from a radioactive isotope; and a signal processor that generates a random number based on an absorption event at which the plurality of emission particles are absorbed into the plurality of cells, and thus new type of random number conversion method that combines a spatial randomness and existing temporal randomness of the emission particle can be provided, there is no restriction generated due to the dead time, the random number generation rate can be remarkably increased, and it is possible to generate of a pure random number at high speed, which is required by a computer, a network processor, or an IoT device.

Abstract: A computer-implemented method for Eigenpair computation is provided. The method includes computing, her a hardware processor, an Eigenvector and respective Eigenvalues of the Eigenvector of a matrix by using a modified Stochastic Optimization process including performing a matrix vector product on a Resistive Processing Unit (RPU) crossbar array operatively coupled to the hardware processor and performing a scalar vector product on a digital device operatively coupled to the hardware processor and representing, for each of an Eigenpair, an initial guess for the Eigenvector and the respective Eigenvalues. The computing step includes storing the matrix in the RPU crossbar array.

Abstract: A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.

Abstract: Systems, methods, and apparatuses relating to enhanced matrix multiplier architecture are described.

Abstract: A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.

Abstract: The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision is restructured so that a set of sub-adders performs the arithmetic on a respective segment of the operands. More specifically, the adder is restructured, and a decoder determines a generate signal and a propagate signal for each of the sub-adders and routes the generate signal and the propagate signal to a prefix network. The prefix network determines respective carry bit(s), which carries into and/or select a sum at a subsequent sub-adder.

Abstract: Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.

Abstract: A computation unit computes a function f(I). The function f(I) has a target output range over a first domain of an input I encoded using a first format. A first circuit receives the encoded input I in the first format including X bits, to add an offset C to the encoded input I to generate an offset input SI=I+C, in a second format including fewer than X bits. The offset C is equal to a difference between the first domain in f(I) and a higher precision domain of the second format for the offset input SI. A second circuit is operatively coupled to receive the offset input SI in the second format, to output a value equal to a function f(SI) to provide an encoded output value f(I).

Abstract: A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

Abstract: Systems, apparatuses, and methods related to bit string accumulation are described. A method for bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and modifying a quantity of bits of a result of the iteration of the recursive operation, wherein the modified quantity of bits is less than a threshold quantity of bits. The method can further include writing a first value comprising the modified bits indicative of the result of the iteration of the recursive operation to a first register and writing a second value indicative of the factor corresponding to the result of the iteration of the recursive operation to a second register.

Abstract: A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.