Abstract: A device for generating a nondeterministic response to a challenge, the device comprising: a structure that exhibits a nondeterministic electrical output response to an electrical input, the device being arranged to facilitate a challenge of the structure to generate the nondeterministic response, by facilitating an electrical measurement of an output of the structure, the nondeterministic response being derivable from that measurement.

Abstract: A true random number generation system includes a physical unclonable function (PUF) entropy device, a pseudo random number generator, and an encoding circuit. The PUF entropy device is used for generating a random number pool. The pseudo random number generator is used for generating a plurality of first number sequences. The encoding circuit is coupled to the PUF entropy device and the pseudo random number generator for generating a plurality of second number sequences according to the plurality of first number sequences and a plurality of third number sequences selected from the random number pool.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor acquires statistical information on a distribution of bits in floating point number data after executing an instruction on the floating point number data, and converts the floating point number data to fixed point number data.

Abstract: A secure computation system is provided. The system includes a distribution information generation apparatus that generates data distribution values, sign distribution values and carry distribution values from at least two fixed-point numbers by distributing each of the at least two fixed-point numbers using an additive secret sharing scheme; and a secure computation apparatus group including at least two secure computation apparatuses. The secure computation apparatus group includes: a secure digit extender; and a secure multiplier.

Abstract: Disclosed herein is a true random number generator (TRNG). The TRNG includes an enclosure defining a cavity and a cap covering the cavity and having a cap surface exposed to the cavity, the cap surface including radioactive nickel. An electronic sensor within a cavity detects electrons from the decay of the nickel and produces a signal for the detected energy. An amplifier is connected to the sensor and constructed to amplify the signal and feeds the signal to a filter. A processor connected to the filter generates a true random number based on the signal. This TRNG may be formed on an integrated circuit.

Abstract: An electric device for a hardware random number generator is provided. The hardware random number generator comprises: one or more bitcells which comprise a first pair of a first transistor and a first tunable resistor and a second pair of a second transistor and a second tunable resistor, with the first pair is cross-coupled with the second pair.

Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.

Abstract: A true random number generator with a dynamic compensation capacity comprises a loop control logic, a shift register, a sensitive amplifier and a load matching unit. The sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays. Each NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor. The load matching unit comprises a first D flip-flop and a second D flip-flop and is connected at an output terminal and an inverted output terminal of the sensitive amplifier. The true random number generator has the advantages of simple feedback regulation and high robustness.

Abstract: An integrated circuit device such as a neural network accelerator can be programmed to select a numerical value based on a multinomial distribution. In various examples, the integrated circuit device can include an execution engine that includes multiple separate execution units. The multiple execution units can operate in parallel on different streams of data. For example, to make a selection based on a multinomial distribution, the execution units can be configured to perform cumulative sums on sets of numerical values, where the numerical values represent probabilities. In this example, to then obtain cumulative sums across the sets of numerical values, the largest values from the sets can be accumulated, and then added, in parallel to the sets. The resulting cumulative sum across all the numerical values can then be used to randomly select a specific index, which can provide a particular numerical value as the selected value.

Abstract: The present innovative solution solves the problem of generating pseudo-random numbers that have practically infinite period, while requiring limited processing resources and operating significantly faster that known pseudo-random number generators. A sequence of pseudo-random numbers is created by a linear congruential generator using a large seed number and the sequence is used to create a big number. The big number is formed by raising each of at least two pseudo-random numbers and their sum to the same power. The big number is then selectively split into a sequence of aperiodic pseudo-random numbers which are output for use in any suitable application and for seeding the present generator.

Abstract: Techniques for compressing binary input data streams and files by reducing entropy of the input data prior to compression. Entropy reduction is achieved by first getting a stream of single-digit decimal pseudo random numbers and calculating the frequency of occurrence of each decimal number in the even and odd positions of the pseudo random number stream. Subsets of the frequencies of occurrence of the decimal digits are selected to best match the frequency of occurrence of “0” and “1” in the odd and even positions of the binary input data stream. The decimal digits of the subsets of frequencies of occurrence are selectively set to “0” or “1” thereby creating a binary pseudo random number (i.e. mapping) stream, which is XORed with the binary input stream and compressed. Decompression uses the same pseudo random number stream using the mapping stream and the seed number used during compression.

Abstract: Disclosed herein is a true random number generator (TRNG). The TRNG includes an enclosure defining a cavity and a cap covering the cavity and having a cap surface exposed to the cavity, the cap surface including radioactive nickel. An electronic sensor within a cavity detects electrons from the decay of the nickel and produces a signal for the detected energy. An amplifier is connected to the sensor and is constructed to amplify the signal and then feeds the signal to a filter. A processor connected to the filter generates a true random number based on the signal. This TRNG may be formed on an integrated circuit.

Abstract: An electronic circuit for Random Number Generation (RNG) includes a first inverter having a first input and a first output, and a second inverter having a second input and a second output. The first output is connected to the second input, and the second output is connected to the first input. A switch is configured to (i) when closed, to set the first and second inverters to a meta-stable state by shorting the first output to the first input and the second output to the second input, and (ii) when open, to release the first and second inverters from the meta-stable state to a bi-stable random state. Logic circuitry is configured to alternately close and open the switch, and to output random values from at least one of the first and second inverters when at the bi-stable random state.