Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: A neural network processor for performing a neural network operation may include a memory storing computer-readable instructions, and kernel intermediate data, the kernel intermediate data including a plurality of kernel intermediate values calculated based on a plurality of weight values included in kernel data; and at least one processor to execute the computer-readable instructions to perform a convolution operation by selecting at least one kernel intermediate value among the plurality of kernel intermediate values based on an input feature map.

Abstract: Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

Abstract: A photonic random signal generator includes an incoherent optical source configured to generate an optical noise signal, a filter configured to generate a filtered optical noise signal using the optical noise signal, a coupler, a photodetector, a filter, and a limiter. The coupler couples the filtered optical noise signal and a delayed version of the filtered optical noise signal to generate a first coupled signal and a second coupled signal. The photodetector generates an output signal representative of a phase difference between the filtered optical noise signal and the delayed version of the filtered optical noise signal using the first coupled signal and the second coupled signal. The filter filters the output signal representative of the phase difference to generate an analog random signal. The limiter thresholds the analog random signal based on a clock signal, to generate a digital random signal.

Abstract: A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

Abstract: The present disclosure relates to a matrix transposition device and method, and a display device. The matrix transposition device includes a first counting unit, an input module, second counting units, and a first data selection unit. The first counting unit numbers a matrix element and outputs a first signal. The input module is coupled to the first counting unit, and is input with the matrix element after receiving the first signal; each. Each column of matrix elements corresponds to one of the second counting units, each of the second counting units outputs a set of second signals, and each set of the second signals includes number information of the matrix elements in a column corresponding to the second counting unit. The first data selection unit receives the second signals in an order of columns of a matrix, and orderly outputs column elements of the matrix as row elements of a transposed matrix.

Abstract: The present disclosure advantageously provides a system, matrix multiply accelerator (MMA) and method for efficiently multiplying matrices. The MMA includes a vector register to store the row vectors of one input matrix, a vector register to store the column vectors of another input matrix, a vector register to store an output matrix, and an array of vector multiply and accumulate (VMAC) units coupled to the vector registers. Each VMAC unit is coupled to at least two row vector signal lines and at least two column vector signal lines, and is configured to calculate the dot product for one element i,j of the output matrix by multiplying each row vector formed from the ith row of the first matrix with a corresponding column vector formed from the jth column of the second matrix to generate intermediate products, and accumulate the intermediate products into a scalar value.

Abstract: A method and a MAC unit that may include accumulation unit and a multiplier. A accumulation unit that includes a first part, a second part and a third part. The first part may calculate a truncated sum. The second part may be configured to (a) receive, during each calculation cycle, a carry out of an add operation performed during a calculation cycle, (b) receive a sign bit of an intermediate product calculated during the calculation cycle; and (c) calculate, by the counter logic, a counter logic value, and (d) convert, after a start of a last calculation cycle of the calculation cycles, an output value of the counter logic to an intermediate value having a two's complement format. The third part may be configured to calculate an output value of the MAC unit based on the intermediate value and a truncated sum calculated by the first part of the accumulation unit.

Abstract: A method of verifying randomness of a bitstream is disclosed. The method includes receiving a bitstream consisting of n consecutive bits and dividing the bitstream into a plurality of bit blocks. In this case, n is a natural number of two or greater, each of the bit blocks consists of m consecutive bits, and m is a natural number of two or greater and is smaller than n. Further, the method includes allocating the plurality of bit blocks to a plurality of core groups in a graphics processing unit (GPU), processing the allocated bit blocks in the plurality of core groups in parallel, calculating random number level values of the allocated bit blocks, and determining whether the bitstream has randomness based on the calculated random number level values. Each of the core groups includes a plurality of cores capable of performing identical or similar tasks without separate synchronization.

Abstract: A non-maximum suppression operation device and system; the non-maximum suppression operation device includes: a data access module to import external data or export a non-maximum suppression computation result of the external data; a control module to send a control signal for performing a computation on the external data; and an operation module to perform an intersection-over-union computation on the external data on the basis of the control signal to obtain an intersection-over-union computation result, and to compare the intersection-over-union computation result with a preset threshold value to obtain the non-maximum suppression computation result.

Abstract: An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Abstract: An in-memory multiply and accumulate circuit includes a memory array, such as a NOR flash array, storing weight values Wi,n. A row decoder is coupled to the set of word lines, and configured to apply word line voltages to select word lines in the set. Bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values Xi,n on the corresponding inputs. Current sensing circuits are connected to receive currents in parallel from a corresponding multimember subset of bit lines in the set of bit lines, and to produce an output in response to a sum of currents.

Abstract: According to examples, an apparatus may include a processor and a non-transitory computer readable medium having instructions that when executed by the processor, may cause the processor to partition a matrix of elements into a plurality of sub-matrices of elements. Each sub-matrix of the plurality of sub-matrices may include elements from a set of columns of the matrix of elements that includes a nonzero element. The processor may also assign elements of the plurality of sub-matrices to a plurality of crossbar devices to maximize a number of nonzero elements of the matrix of elements assigned to the crossbar devices.

Abstract: A multiply-accumulate (MAC) operation in a deep neural network (DNN) consists of multiplying each input signal to a node by a respective numerical weight data and summing the products. Using ternary values for the input signals and weight data reduces memory and processing resources significantly. By representing ternary values in two-bit binary form, MAC operations can be replaced with logic operations (e.g., XNOR, popcount) implemented in logic circuits integrated into individual memory array elements in which the numerical weight data are stored. In this regard, a ternary computation circuit (TCC) includes a memory circuit integrated with a logic circuit. A memory array including TCCs performs a plurality of parallel operations (e.g., column or row elements) and determines a popcount. A TCC array in which logic circuits in columns or rows employ a single read-enable signal can reduce routing complexity and congestion of a metal layer in a semiconductor device.

Abstract: An execution unit is described which is particularly configured to generate an exponential of an operand floating point format. The operand is multiplied by a fixed multiplicand, logged to the base 2 (e) to generate a multiplication result. An integer part and a fractional part are extracted from the multiplication result. An exponent register stores the integer part to form the exponent of the exponential result. A lookup table has a plurality of entries each providing a value of 2f for a fractional part f used to access a lookup table. The fractional part is derived from a mantissa of the operand. That is, first and second bit sequences are extracted from the mantissa. One of the bit sequences is used to generate an estimated fractional component, and the other is used to access a value from the lookup table.

Abstract: Predictive regression models are widely used in different domains such as life sciences, healthcare, pharma etc. and variable selection, is employed as one of the key steps. Variable selection can be performed using random or exhaustive search techniques. Unlike a random approach, the exhaustive search approach, evaluates each possible combination and consequently, is a computationally hard problem, thus limiting its applications. The embodiments of the present disclosure perform i) parallelization and optimization of critical time consuming steps of the technique, Variable Selection and Modeling based on the Prediction (VSMP) ii) its applications for the generation of the best possible predictive models using input dataset (e.g., Blood Brain Barrier Permeation data) and iii) business impact of predictive models that are requires the selection of larger number of variables.

Abstract: A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.

Abstract: Systems, apparatuses, and methods related to host-based bit string conversion are described. A conversion component may be deployed on a host computing system and configured to perform operations on bit strings to selectively convert the bit string between various numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The conversion component may comprise a processing device that may be coupled to one or more memory resources. The memory resource of the conversion component may be configured to receive a bit string having a first format. The processing device of the conversion component coupled to the memory resource may be configured to format or convert the bit string to a second format.

Abstract: A Random Number Generator includes a photon source, one or more photon detectors configured to detect at least one photon belonging to a flow of detected photons (?) generated by the photon source, an electronic sampler operatively associated with the photon detectors and configured to implement a logic method for the extraction of a binary sequence based on the arrival time of each one of the detected photons (?). In the Random Number Generator, the photon source and the photon detectors are adjacent to one another and integrated in a single semiconductor substrate.

Abstract: The present innovative solution solves the problem of generating pseudo-random numbers that have practically infinite period, while requiring limited processing resources and operating significantly faster that known pseudo-random number generators. A sequence of big pseudo-random numbers is created using a large seed number calculated as the product of three large constants entered by a user or fed by a computer clock. The big pseudo-random numbers are then selectively split into a sequence of aperiodic pseudo-random numbers which are then output for use in any suitable application and for seeding the present generator.