Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.

Abstract: A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.

Abstract: A duty cycle detection circuit, comprises a charge storage component and compare logic. The charge storage component has at least one capacitor, at least one switch, and, at least one current source. A clock signal is used to operate the at least one switch for charging the at least one capacitor using the at least one current source. The charge storage component outputs a first signal indicative of an amount of charge stored when the clock signal is logic high and a second signal indicative of an amount of charge stored when the clock signal is logic low. The compare logic compares the first signal and the second signal to determine a duty cycle for the clock signal.

Abstract: A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

Abstract: A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

Abstract: A straight tube LED lamp includes: a straight tube in which a plurality of light emitting diodes is housed; a first cap for forming a power feeding connection to the plurality of light emitting diodes, provided on one axial direction end side of the straight tube; and a second cap for grounding, provided on another axial direction end side of the straight tube. A first terminal for forming an electrical connection to a power feeding terminal of a first lamp socket is provided in the first cap. A second terminal for forming an electrical connection to a grounding terminal of a second lamp socket is provided in the second cap.

Abstract: A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and del

Abstract: A digital control loop circuit is disclosed which is coupleable to an oscillator to form a configurable, digital phase-locked loop to generate an output signal having a configurable or selectable output frequency. A representative embodiment of the digital control loop circuit may include a memory storing a plurality of configuration parameters, at least one configuration parameter specifying the output frequency; and a digital controller coupleable to receive an input signal from a reference frequency generator having a reference frequency, the digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the oscillator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.

Abstract: In an embodiment, semiconductor switch includes first switches switching conduction between input-output nodes and a common node. One of the first switches includes a plurality of first transistors connected in series between an input and output node and the common node. Each of the plurality of first transistors includes first gate electrodes, a second gate electrode, a first and second region in a semiconductor layer having a same conduction type. The first gate electrodes extend in parallel in a first direction. The second gate electrode extending in a direction crossing the first direction and is connected to one end of the first gate electrodes. The second region in the semiconductor layer is disposed on a side of the second gate electrode opposite to the first gate electrodes.

Abstract: A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected.

Abstract: A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.

Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example method may include providing an output clock signal responsive to an input clock signal, and adjusting a slew rate of the output clock signal by a delayed output clock signal.

Abstract: A light source apparatus according to the present invention, includes: a light source substrate on which one or more emission units are located; an optical sheet configured to reflect light from the emission unit; and a detection unit configured to detect reflected light reflected by the optical sheet, wherein the detection unit is located in a position where an amount of change in a detected value due to deflection of the optical sheet when one emission unit is turned ON is a predetermined value or less.

Abstract: A skew reduction circuit includes a first delay circuit that delays a first clock signal to generate a second clock signal and a second delay circuit that delays a third clock signal to generate a fourth clock signal. The skew reduction circuit also includes a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals. The skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew.

Abstract: A spread spectrum clock generator includes: a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal; a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal; a delta-sigma modulator that receives a waveform signal for controlling spreading of a spectrum of the output clock signal, and outputs bits larger than 1 bit based on the waveform signal; a control circuit that controls a multiplication number according to an output signal of the delta-signal modulator; and a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit.

Abstract: An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses.

Abstract: A driver circuit for turning ON and OFF one of two parallel-connected insulated-gate semiconductor elements includes a voltage control circuit that controls a level of a power supply voltage in response to a detected element temperature of the one semiconductor element, a constant current supply section, responsive to a drive signal, for supplying a constant current to a gate of the one semiconductor element to turn the one semiconductor element ON, the power supply voltage being supplied to the constant current supply section from the voltage control circuit, and a discharge circuit, responsive to the drive signal, for discharging an electric charge accumulated in the gate to turn the one semiconductor element OFF.

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

Abstract: The present disclosure provides a single-phase PLL controlling method and a single-phase PLL controlling device. The device includes a first FIR filter, a second FIR filter and a Park converter. The first FIR filter and the second FIR filter are configured to perform FIR filtration on a collected power grid voltage signal so as to acquire filtered signals, and output the filtered signals to the Park converter. A filtered signal V? acquired by the first FIR filter and a filtered signal V? acquired by the second FIR filter form a set of virtual two-phase signals in an ?? coordinate system. The Park converter is configured to perform Park conversion on the filtered signal V? and the filtered signal V?, so as to acquire a set of two-phase signals Vd and Vq in a dq coordinate system.