Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

Abstract: Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.

Abstract: A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained.

Abstract: A receiving circuit may include a wide range receiving circuit and a parallelizing circuit. The wide range receiving circuit may amplify an input signal which swings within a first range and generate an intermediate output signal which swings within a second range wider than the first range. The parallelizing circuit may compare the intermediate output signal with a second reference voltage and amplify the intermediate output signal accordingly and generate output signals which swing within a third range wider than the second range.

Abstract: A circuit device includes a drive circuit that drives a physical quantity transducer, an FLL circuit that includes a frequency comparator and an oscillator, and generates a clock signal with a signal from the drive circuit as a reference clock signal, and a detection circuit that includes a circuit operated based on the clock signal, and performs detection processing on a detection signal from the physical quantity transducer.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: A semiconductor integrated circuit apparatus may include a clock-distributing unit, an internal circuit unit and an output-controlling unit. The clock-distributing unit may drive an input clock to output a distribution clock. The internal circuit unit may generate an internal circuit output signal in response to an input signal and the distribution clock. The output-controlling unit may select one of the input clock and the distribution clock in response to a clock selection signal and an output selection signal. The output-controlling unit may synchronize the internal circuit output signal with a clock selected between the input clock and the distribution clock or bypass the internal circuit output signal to output an output signal.

Abstract: A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.

Abstract: The phase-locked loop (PLL) presented herein controls the phase of the output of the PLL. To that end, the PLL includes an oscillator that generates an output signal at an output of the PLL responsive to a comparison between a reference signal input to the PLL and a feedback signal derived from the output signal. To control the phase of the output signal, a modulation signal is applied to one input of the oscillator, separate from the reference signal input, where the modulation signal comprises one or more pulses having a total area defined based on the desired phase shift. To maintain the desired phase shift at the output of the PLL, the PLL also sets a time relationship between the reference signal and the feedback signal based on the desired phase shift.

Abstract: Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in a closed loop configuration and can use the calibrated delay settings to locally self-generate a recovered clock at the destination during a locked state. During the locked state, clock buffers in the clock distribution network can be powered down to save power.

Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Abstract: A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out falling edge according to an old phase interpolator code input, disabling a falling edge ramp signal while updating a falling edge interpolator, enabling the rising edge ramp signal and generating a new clock out rising edge according to a new phase interpolator code input, and enabling the falling edge ramp signal and generating a new clock out falling edge according to the new phase interpolator code input.

Abstract: A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.

Abstract: A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.

Abstract: A circuit and a method for controlling operation voltage, and a storage device are provided. The circuit includes: a voltage boost unit adapted for: if receiving a first signal, performing a voltage boost process; and if receiving a second signal, stopping the voltage boost process; a voltage division unit including a plurality of different voltage division coefficients, adapted for performing a voltage division process; a comparison unit adapted for: comparing the divided voltage with a reference voltage; if the divided voltage is low, outputting the first signal; and if not, outputting the second signal; a control unit adapted for performing a descending switching operation on the voltage division coefficients; and an output unit. The establishing speed of the operation voltage is effectively controlled, and an effect on device power consumption and performance caused by the threshold voltage and variations of the threshold voltage in the working process is eliminated.

Abstract: A digital controlled oscillator (DCO) is provided that includes a plurality of selectable delay cells, a first load adjustment delay (LAD) cell, a second LAD cell, a first set of the load cells (LCs), a second set of the LCs and first and second capacitance elements. A number of the selectable delay cells that are part of a delay cell chain is configurable based on a delay cell number control vector. The delay cell chain generates a delay cell output signal that is received by the first LAD cell. The first set of the LCs generate a first load signal to control an amount of loading on the second LAD cell, and the second set of the LCs generate a second load signal to control loading on the first LAD cell. Substrate voltages of the first and second capacitance elements can be adjusted to adjust loading in the DCO.

Abstract: A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch.