Abstract: A network device may be operable to receive an indication from a cable modem termination system (CMTS) that media access control (MAC) management messages will be transmitted by the CMTS at fixed intervals. Subsequent to receiving the indication, the network device may be operable to power down one or more components of the network device and set a sleep timer to a value equal to an integer multiple of the fixed interval minus a transition period. The network device may power up the one or more components of the network device upon expiration of the sleep timer. The network device may power up the one or more components of the network device upon an amount of traffic in a buffer of the network device reaching a threshold.

Abstract: According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract: Disclosed herein are a server and an inspecting method thereof. The server comprises a baseboard management controller (BMC), a non-volatile memory coupled with the baseboard management controller, and a basic input/output system. After the server is powered on, the basic input/output system starts running, performs power-on self-test for the server to generate current hardware configuration data. The BMC then determines whether preset hardware configuration data, stored beforehand in the non-volatile memory, and the current one agree. If the preset and the current hardware configuration data have one or more mismatches, the BMC records the mismatch or mismatches in an event log.

Abstract: A storage control system, and a method of operation thereof, including: a host interface module for receiving a host command from a host system; a power measurement module, coupled to the host interface module, for reading a current value of an electrical power supplied by the host system in response to the host command; and a schedule module, coupled to the power measurement module, for scheduling new operations to be executed in parallel in non-volatile memory devices, the new operations are scheduled when the current value of the electrical power does not exceed a power limit.

Abstract: A power management system that can include an application processor and a power management unit (PMU). The PMU can generate a regulated output voltage based on control signals generated by a switch control module of the application processor. The control signals can be determined based on a comparison of monitored voltages within the application processor and a generated reference voltage. The reference voltage can be generated based on fed back signals corresponding to the control signals. The application processor and the PMU can be formed utilizing different size manufacturing process technologies. For example, the PMU can be formed utilizing a larger size manufacturing process technology than the application processor.

Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.

Abstract: Techniques and mechanisms allow for implementing multiple configuration profiles for dynamic reconfiguration of an Intellectual Property (IP) core. A minimum set of data may be generated, as well as detecting errors between the configuration profiles.

Abstract: An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops.

Abstract: This invention relates to a modular combined optical data and electrical power distribution network and related system. More particularly the invention relates to a system for bi directional high-speed distribution of data and the universal transmission of significant quantities of electrical power using composite cabling which is adapted for connection to a plurality of peripheral components and devices. Previous data networks, particularly in domestic environments, for example for controlling personal computers, laptops and peripherals such as printers and scanners required dedicated power supplies and resulted in a tangled mass of wires and cabling often seen as clutter and sometimes posing safety hazards. The invention overcomes this problem by providing a relatively low voltage continual power bus, in the form of a dual or multi-core wire, which typically carries up to 100-200 Watts per node and which is also capable of carrying high volumes of data traffic typically in excess of 1 GBit/sec.

Abstract: A computer system is disclosed. When a user conducts different operations on a switch module, a switch module generates different clicking indication signal, and a logic control module generates a corresponding signal according to clicking indication signals so that a management control module processes a signal generated by a logic control module. As such, a single switch may be used to trigger multiple functions, whereby achieving in the efficacy of saving a design cost of a server panel.

Abstract: A method for updating configuration information includes, in a computing device including a processor, memory, and an operating system, initiating an update to at least one configuration setting of the computing device. The update may be downloaded from at least one update data source. The update may include configuration update data and configuration update metadata. The update may be verified by comparing the configuration update metadata with metadata associated with a current version of the at least one configuration setting. The update may be installed if it is verified. The update to the at least one configuration setting may be installed based on an intent from an unsecure component of the computing device. The unsecure component may include content consuming application installed on the device, a component of a computing platform of the device, and/or an update-seeker application installed on the device.

Abstract: Methods, systems and computer program products are disclosed for enhanced system boot processing that is faster to launch an operating system, as certain devices such as user input hardware devices may not be initialized unless it is determined that a user-interruption to the boot process is likely. That is, although an interface for the devices is exposed, no initialization occurs unless a call to the interface occurs. Other embodiments are described and claimed.

Abstract: A microcontroller has a plurality of peripherals, and at least one control bit, wherein the control bit controls a reset of at least one peripheral such that in a first mode any type of reset resets the at least one peripheral of said plurality of peripherals and in a second mode only a power supply reset resets the at least one peripheral.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced.

Abstract: A microcontroller system includes a reset delaying module that is configured to, during a power saving mode, receive and delay a reset signal from a reset source. The reset delaying module waits for a regulator ready signal from a voltage regulator because, prior to the reset signal, the voltage regulator is in a power saving mode. In response to receiving the regulator ready signal, the reset delaying module releases the reset, e.g., to a reset controller.

Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

Abstract: A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register.