Abstract: A data storage apparatus may include: a storage comprising a plurality of memory blocks; and a controller configured to: configure a write buffer pool by selecting a plurality of first memory blocks which are some of the plurality of memory blocks, manage remaining memory blocks except for the first memory blocks as second memory blocks, exclude one or more of the first memory blocks, whose data are migrated to the second memory blocks and add one or more of the second memory blocks to the write buffer pool.

Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

Abstract: A method for generating a reconstructed version of a filesystem entity, the method may include (i) generating fallback retrieval metadata for a reconstructed version segment, when the reconstructed version segment is (a) associated with a corresponding intermediate version segment, and (b) the corresponding intermediate version segment is preceded by a corresponding most updated segment that does not exceed a fallback version of the filesystem entity; wherein the reconstructed version segment, the corresponding intermediate version segment and the corresponding most updated segment that does not exceed a fallback version have a same address range; (ii) generating a non-existing indicator for the reconstructed version segment, when the reconstructed version segment is (a) associated with the corresponding intermediate version segment, and (b) the corresponding intermediate version segment is not preceded by any corresponding most updated segment that does not exceed the fallback version; and (iii) maintaining

Abstract: Techniques are provided for object store mirroring. Data within a storage tier of a node may be determined as being data to tier out to a primary object store based upon a property of the data. A first object is generated to comprise the data. A second object is generated to comprise the data. The first object is transmitted to the primary data store for storage in parallel with the second object being transmitted to a mirror object store for storage. Tiering of the data is designated as successful once acknowledgements are received from both the primary object that the first object was stored and the mirror object store that the second object was stored.

Abstract: Techniques are provided for object store mirroring. Data within a storage tier of a node may be determined as being data to tier out to a primary object store based upon a property of the data. A first object is generated to comprise the data. A second object is generated to comprise the data. The first object is transmitted to the primary data store for storage in parallel with the second object being transmitted to a mirror object store for storage. Tiering of the data is designated as successful once acknowledgements are received from both the primary object that the first object was stored and the mirror object store that the second object was stored.

Abstract: A semiconductor device includes an address translation device configured to identify a plurality of address translation tables which is used for address translation having a plurality of stages; and an adder configured to identify a stage in the address translation when executing the address translation, wherein the address translation device configured to perform cache control for information of a first address translation table used in a last stage of the address translation when the stage is the final stage.

Abstract: Aspects of the present disclosure relate to asynchronous memory management. In embodiments, an input/output (IO) workload is received at a storage array. Further, one or more read-miss events corresponding to the IO workload are identified. Additionally, at least one of the storage array's cache slots is bound to a track identifier (TID) corresponding to the read-miss events based on one or more of the read-miss events' two-dimensional metrics.

Abstract: A method for tracking a progress of data copying for a live migration includes transferring, by a storage controller, a first data structure to a live migration server, the first data structure including a first status identifier indicating a location of a source data to be copied from a source storage to a target storage, and selectively generating or selectively clearing, by the storage controller, a second status identifier in or from a second data structure, based on a first current copying location of the live migration server, the second status identifier indicating a location of a first user data write to the source storage.

Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.

Abstract: A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.

Abstract: Storage efficiency driven migration includes: determining a level of similarity between first data stored on a first storage system and second data stored on a second storage system; determining, in dependence upon the level of similarity, that an expected amount of storage space reduction from migrating similar data exceeds a threshold level; and responsive to determining that the expected amount of storage space reduction exceeds the threshold level, initiating a migration of one or more portions of the first data from the first storage system to the second storage system.

Abstract: An information handling system includes a first storage array having a first logical block table with logical block addresses. Each logical block address includes a pointer to an associated data block in a first storage volume of the first storage array. The second storage array includes a second logical block table having the logical block addresses and a second storage volume. The first storage array receives a data read command from the second storage array to a first logical block address, and in response to the data read command, determines that a data block pointed to by the first logical block address in the first storage array is also pointed to by second logical block address that is adjacent to the first logical block address in the first logical block table, and sends the data block and metadata to the second storage array, the metadata indicating that the second logical block address points to the data block.

Abstract: Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.

Abstract: A storage system has a plurality of heterogenous storage nodes characterized by non-uniform total non-volatile storage capacity. Storage capacity of all nodes is configured as same-size cells and represented as a set of matrices. The matrices have dimensions corresponding to consecutive cell indices and consecutive storage node indices. Initially, storage nodes having the same storage capacity are consecutively indexed so that the representative matrices are not ragged due to gaps, referred to herein as non-contiguous storage space, where cells do not exist because of differences in numbers of cells in adjacently indexed storage nodes. Addition of more heterogeneous storage nodes can create such gaps when the cells of those storage nodes are added to the matrices.

Abstract: A block of a storage device of a plurality of storage devices is allocated for storage of data, wherein the allocation comprises identifying a nonce associated with the block of the storage device. An erase command for the block is transmitted to the storage device, the erase command comprising the nonce, wherein the storage device is to erase the block upon determining that the nonce matches a corresponding nonce stored locally at the storage device.

Abstract: Data migration from a legacy data storage system into an ordered event stream (OES) data storage system is disclosed. In contrast to conventional techniques, the disclosed subject matter can provide for migrating legacy data into a first portion of a vintage OES (VOES) and new data, intended for the legacy data storage system during the migration process, into a second portion of the VOES. The first and second portions of the VOES can then be linked at completion of the migration process. Avoiding writing new data to the legacy data storage system prior to migration enables a corresponding reduction in data access disruption. Moreover, event sequencing by separating migrated legacy events from new events can preserving event order. Scaling of vintage streams can be supported. Vintage streams can support function calls to a single VOES in contrast to the more conventional use of multiple streams.

Abstract: A memory system includes a memory device including memory blocks, each memory block including a memory cell capable of storing a multi-bit data item. The memory device includes a write booster region including at least one memory block among the plurality of memory blocks, the at least one memory block including a memory cell storing a single-bit data item. A controller is configured to assign a memory block in the write booster region to a host performance booster (HPB) region when the memory block is closed and transmit to a host an indication that the memory block is assigned to the HPB region.

Abstract: Techniques for estimating performance metrics of standalone or clustered storage systems. The techniques include receiving a request from a storage client for an estimated capacity or capability of a storage system to handle a specified workload pattern within a specified periodicity interval, in which the estimated capacity or capability of the storage system is represented by a headroom metric. The techniques further include, in response to the request from the storage client, obtaining a value of the headroom metric for the specified periodicity interval using a performance model characterized by at least a peak load reserve (PLR) metric and a long-term load reserve (LLR) metric, in which the obtained value of the headroom metric corresponds to the minimum of respective values of at least the PLR metric and the LLR metric. The techniques further include upgrading, scaling-up, and/or scaling-out the storage system based on the value of the headroom metric.

Abstract: A method for performing a backup operation includes obtaining, by a backup agent, a backup request for a file system, and in response to the backup request: generating a first application partition for an application associated with the file system, performing a dependency analysis on the application to identify application dependency information, populating a first application partition with a copy of the application dependency information and a copy of application data associated with the application, and initiating a storage of a backup to a backup storage system, wherein the backup comprises the first application partition.

Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.