Abstract: Techniques for implementing and/or operating an apparatus, which includes a memory system coupled to a processing system via a memory bus. The memory system includes hierarchical memory levels and a memory controller. The memory controller receives a memory access request at least in part by receiving an address parameter indicative of a memory address associated with a data block from the memory bus during a first clock cycle and receiving a context parameter indicative of context information associated with current targeting of the data block from the memory bus during a second clock cycle, instructs the memory system to output the data block to the memory bus based on the memory address indicated in the address parameter, and predictively controls data storage in the hierarchical memory levels based at least in part on the context information indicated in the context parameter of the memory access request.

Abstract: Embodiments of the present disclosure provide a method, device, and computer program product for managing cache. There is provided a method of managing a cache, comprising: receiving a current operation request from a user, data requested by the current operation request being to be duplicated to the cache; obtaining a plurality of historical operation requests of the user, the plurality of historical operation requests being received prior to the current operation request; determining a predicted operation request for the user based on the plurality of historical operation requests and the current operation request; and in accordance with determining that a type of an operation associated with the predicted operation request belongs to predetermined types, adjusting data in the cache based on the predicted operation request.

Abstract: A storage-based migration is performed in a VVOL environment. A migration processing unit generates a migration group in which a virtual volume to be migrated, a protocol endpoint related to the virtual volume, and a storage container that cuts out the virtual volume are grouped, and migrates the migration group to a storage node; and a configuration changing unit configures, based on information of the migration group transmitted from the storage node, a protocol endpoint, a virtual volume, and a storage container on a storage node which are the same as the protocol endpoint, the virtual volume, and the storage container configured on the storage node.

Abstract: A method includes obtaining data from a plurality of data sources associated with an n-gram indexing data structure and storing at least a portion of the obtained data in a first storage, the stored data comprising one or more n-gram strings. The method also includes estimating frequencies of occurrence of respective ones of the n-gram strings in the stored data, the estimated frequency of occurrence of a given n-gram string being based at least in part on a size of a given n-gram index in the n-gram indexing data structure corresponding to the given n-gram string. The method further includes, in response to detecting one or more designated conditions, selecting a portion of the stored data based at least in part on the estimated frequencies and moving the selected portion of the stored data from the first storage to a second storage having different read and write access times.

Abstract: Techniques provide for Redundant Array of Independent Disks RAID type conversion. Such techniques involve: determining, based on a type of the target RAID, a plurality of storage spaces from a plurality of available storage disks for forming the target RAID; copying data from a first storage block of a source RAID to a corresponding second storage block in the plurality of storage spaces, wherein a first logical block address of the first storage block in the source RAID is identical to a second logical block address of the second storage block in the target RAID; determining at least one address reference associated with the first storage block; and updating the at least one address reference to point to the second storage block.

Abstract: An electronic device includes a storage device having migration performance of an improved speed. The storage device includes a memory device including a normal memory block and a buffer memory block for temporarily storing data that is to be migrated to the normal memory block and a memory controller configured to control the memory device to migrate the data, which is stored in the buffer memory block, to the normal memory block in response to a migration request received from a host, the memory controller changing a target memory block, in which the data is to be stored, from a first memory block to a second memory block according to whether an operation corresponding to the migration request is delayed or not, while migrating the data to the normal memory block, the first memory block and the second memory block being included in the normal memory block.

Abstract: A method for managing data includes obtaining, by a hypervisor on a host computing device, a write request for storing first data, and in response to the write request: identifying a first set of memory segments associated with the first data using a memory mapper, wherein the first set of memory segments is associated with a memory device, making a first determination that the memory device is local to the host computing device, and in response to the first determination: storing the first data in the first set of memory segments.

Abstract: The present disclosure includes a memory system, a memory controller, and an operation method thereof. The memory system may cache a subset of all map segments in a mapping table indicating mapping information between logical addresses and physical addresses in a map cache, may select map segments on which locking is to be set from the map segments cached in the map cache so as not to be evicted from the map cache based on information on all commands received from a host during a set period of time, and may set lock flags for the map segments on which locking is to be set. Accordingly, the memory system may reduce the overhead occurring in reloading previously evicted map segments in the process of updating a mapping table, and may optimize update performance for a mapping table within a limit that guarantees caching performance to a predetermined level or higher.

Abstract: In a method for managing a storage device in a storage system, a client may send, based on an obtained start address that is of a queue of an NVMe storage device and to which an access request points and an obtained logical address that is of the NVMe storage device and to which the access request points, a remote direct memory access command to a storage node in which the NVMe storage device is located.

Abstract: A storage device includes a storage subsystem and a logical/physical storage location mapping database that maps LAAs to PAAs that identify physical locations in the storage subsystem. A storage controller receives a storage device mapping granularity configuration command from a host that identifies a number of LBAs to associate with a plurality of LAAs and, in response, associates each of the plurality of LAAs with the number of LBAs identified in the command. The storage controller then writes data to a PAA that includes a data size that is equal to a combined LBA size of the number of LBAs that were identified in the command and associated with each of the plurality of LAAs and maps, in the logical/physical storage location mapping database, the PAA to one of the plurality of LLAs that is associated the number of LBAs identified in the command.

Abstract: A data storage device may include a memory device including a plurality of memory blocks having a plurality of free memory blocks and a controller configured to control an operation of the memory device, wherein the controller performs a block allocation operation of allocating one or more free memory blocks among the plurality of free memory blocks as one or more programmable memory blocks, and performs a garbage collection (GC) error defense operation of checking whether a GC operation for the plurality of memory blocks has performed successfully, in response to the block allocation operation.

Abstract: A memory tile, in a local memory, may be considered to be a unit of memory structure that carries multiple memory elements, wherein each memory element is a one-dimensional memory structure. Multiple memory tiles make up a memory segment. By structuring the memory tiles, and a mapping matrix to the memory tiles, within a memory segment, non-blocking, concurrent write and read accesses to the local memory for multiple requestors may be achieved with relatively high throughput. The accesses may be either row-major or column-major for a two-dimensional memory array.

Abstract: A data storage system may have a number of data storage devices that each have a non-volatile memory connected to different first and second memory buffers. A data storage device can consist of a non-volatile memory where a data sector is stored. A network controller can consist of a buffer module connected to a first memory buffer and a second memory buffer that receives a data read request from the host for the data sector and evaluates the first and second memory buffers as a destination for the data sector after the data sector arrives at the buffer module. The buffer module may choose the first memory buffer and store the data sector in the first memory buffer prior to providing the data sector to the host to satisfy the data read request from the first memory buffer.

Abstract: Aspects of a storage device including a cache having a logical-to-physical (L2P) mapping table, a scratchpad buffer, and a controller are provided to optimize cache storage of L2P mapping information. A controller receives a random pattern of logical addresses and identifies each logical address within one of multiple probability distributions. Based on a frequency of occurrence of each logical address, the controller stores a control page including the logical address within either a partition of the L2P mapping table which is associated with the corresponding probability distribution, or in the scratchpad buffer. The frequency of occurrence of each logical address is determined based on whether the logical address is within one or more standard deviations from a mean of each probability distribution. As a result, frequently occurring control pages are stored in cache, while infrequently occurring control pages are stored in the scratchpad buffer.

Abstract: A computer-implemented method, according to one embodiment, is for managing data received at a storage device. The computer-implemented method includes: receiving data management policies, and receiving two or more connection names from a host. Each of the connection names is correlated with one or more of the data management policies. Moreover, a connection path which extends between the storage device and the host is created. The connection path also has a connection name which corresponds thereto. Data is received along the connection path, and the connection name which corresponds to the connection path is matched to one of the connection names received from the host. Furthermore, the received data is processed according to the one or more data management policies that are correlated with the matching one of the connection names received from the host.

Abstract: In a storage system having a controller constructing a provision volume provided to a server system and an addition volume in which data to be stored in the provision volume is added and stored, when a provision volume copying instruction is received, the controller inserts a start marker indicating start time point of copying into address change history information and copies address conversion information of a provision volume while receiving update data to a provision volume from the server system, as address conversion information of a copy-destination volume. On the basis of a start marker of address change history information and history information, a change from start to completion of copying of the address conversion information of a copy-destination volume is reset to a state at the start time point of copying.

Abstract: A request to write a first data item associated with a first thread to a memory device is received. The memory device includes a first portion and a second portion. The first portion includes a cache that includes a first block to be utilized for data caching and a second block and a third block to be used for block compaction. The second block is associated with a high modification frequency and the third block is associated with a low modification frequency. In response to determining a first memory page in the first block is available for writing the first data item, the first data item is written to the first memory page. A determination is made that a memory page criterion associated with the first thread has been satisfied.

Abstract: A memory system is provided to include a first storage device including a first memory device and a first memory controller configured to receive, from a host external to the first storage device, a request including a logical address corresponding to the request; and a second storage device including a second memory device and a second memory controller coupled to receive a request from the first storage device and to control the second memory device, wherein the first memory controller is configured to select a target address among candidate addresses and map the logical address received from the host to the target address, and wherein the candidate addresses include first physical addresses corresponding to the first memory blocks and virtual addresses corresponding to the second memory blocks included in the second memory device.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Techniques manage metadata. Such techniques involve: in response to receiving a request for accessing metadata in a first page, determining, from a plurality of storage units including pages for storing metadata, a storage unit where the first page is located, the plurality of storage units including a first storage unit and a second storage unit, an access speed of the second storage unit exceeding an access speed of the first storage unit; accessing, from the determined storage unit, the first page for metadata; in response to the first page being accessed from the first storage unit, determining whether hotness of the first page exceeds a threshold level; and in response to the hotness of the first page exceeding the threshold level, transferring the first page from the first storage unit to the second storage unit. Accordingly, such techniques can improve the efficiency for accessing the metadata.