Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.

Abstract: A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.

Abstract: A semiconductor structure and a fabrication method thereof. The semiconductor structure, includes a substrate; and a work function layer on the substrate, that the work function layer contains aluminum and oxygen elements, the work function layer includes a first surface and a second surface opposite to the first surface, a distance between the first surface and a surface of the substrate is less than a distance between the second surface and the surface of the substrate, and along a direction from the first surface to the second surface, a molar percentage concentration of aluminum atoms in the work function layer decreases, and a molar percentage concentration of oxygen atoms in the work function layer decreases. The semiconductor structure can improve the ability to adjust the threshold voltage of a device, thereby improving the performance of the formed semiconductor structure.

Abstract: The present disclosure provides an integrated circuit device that comprises a semiconductor substrate having a top surface; a first and a second source/drain features over the semiconductor substrate; a first semiconductor layer extending in parallel with the top surface and connecting the first and the second source/drain features, the first semiconductor layer having a center portion and two end portions, each of the two end portions connecting the center portion and one of the first and second source/drain features; a first spacer over the two end portions of the first semiconductor layer; a second spacer vertically between the two end portions of the first semiconductor layer and the top surface; and a gate electrode wrapping around and engaging the center portion of the first semiconductor layer. The center portion has a thickness smaller than the two end portions.

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.

Abstract: Disclosed herein are lids for integrated circuit (IC) packages with solder thermal interface materials (STIMs), as well as related methods and devices. For example, in some embodiments, an IC package may include a STIM between a die of the IC package and a lid of the IC package. The lid of the IC package may include nickel, the IC package may include an intermetallic compound (IMC) between the STIM and the nickel, and the lid may include an intermediate material between the nickel and the IMC.

Abstract: A manufacturing method of a display panel, a display panel, and a display apparatus. The manufacturing method includes: forming a plurality of backlight units on a process substrate; filling a partition between adjacent backlight units, where a height of the partition relative to the process substrate is greater than a height of the adjacent backlight units relative to the process substrate; preparing a filter layer on a surface of each of the plurality of backlight units away from the process substrate; stripping the backlight units with the filter layer on surfaces of the backlight units from the process substrate, and transferring to a target substrate; and packaging the target substrate.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: A Compact FINFET System including a material which forms rectifying junctions with both N or P-type Field Induced Semiconductor, including at least two FINS electrically connected thereto and projecting substantially away therefrom parallel to one another. There further being substantially non-rectifying junctions to the material which forms a rectifying junction with both N or P-type Field Induced Semiconductor, and distal ends of the at least two FINS.

Abstract: A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.

Abstract: A hybrid heterostructure includes a semiconductor layer comprising indium antimonide, a superconductor layer comprising aluminum, and a screening layer between the semiconductor layer and the superconductor layer, the screening layer comprising indium arsenide. By including a screening layer of indium arsenide between the semiconductor layer of indium antimonide and the superconductor layer of aluminum, a high-performance and durable hybrid heterostructure suitable for use in quantum computing devices is provided.

Abstract: Provided are metal oxide field-effect transistor (MOSFET) devices having a metal gate structure, in which a work function of the metal gate structure is uniform along a length direction of a channel, and manufacturing methods thereof. The MOSFET devices include a semiconductor substrate, an active area on the semiconductor substrate and extending in a first direction, and a gate structure on the semiconductor substrate. The gate structure extends across the active area in a second direction that traverses the first direction and comprises a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area. A lower surface of the WFC layer may be longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.