Patents Examined by Christopher Bartels
  • Patent number: 10366034
    Abstract: One embodiment is directed to a method of tracking, using an automated infrastructure management (AIM) system, connections made using a breakout cable. The breakout cable comprises a plurality of breakout connectors at a breakout end of the breakout cable. The method comprises identifying a sequence for adding or removing connections involving the breakout connectors of the breakout cable, identifying events associated with adding or removing connections involving the breakout connectors of the breakout cable, and associating the breakout connectors of the breakout cable with added or removed connections based on the identified sequence and the identified events. Other embodiments are disclosed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 30, 2019
    Assignee: CommScope, Inc. of North Carolina
    Inventors: Yu Zhong, Ryan Enge, Lary Blake Van Scoy, LeaAnn Harrison Carl, Michael G. German, Danny L. Satterthwaite
  • Patent number: 10366043
    Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 30, 2019
    Assignee: NXP B.V.
    Inventor: Vinod Kumar Nahval
  • Patent number: 10339079
    Abstract: A host interface communicates with a non-volatile memory (NVM) device over a bus. The host interface includes a first buffer, a second buffer and a scatter/gather list (SGL). The first buffer stores blocks of application data to be communicated to the storage device. The second buffer stores blocks of protection data added by the host interface with respect to the blocks of application data stored in the first buffer. The SGL utilizes a first descriptor type that includes a first buffer address, a first buffer interleave burst length, and a burst count, and a second descriptor type that includes a second buffer address, and a second buffer interleave burst length, wherein only a first descriptor and a second descriptor is required to interleave application data from the first buffer with protection data from the second buffer.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: July 2, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dylan Mark Dewitt, Colin Christopher McCambridge
  • Patent number: 10313236
    Abstract: A method is provided for use with a packet routing network in which one or more endpoints includes Flash storage; multiple endpoints are configured to impart services to packets; a distributed routing structure is provided that includes routing structure portions that are associated with endpoints and that indicate next hop destination endpoint addresses that collectively define multiple sequences of endpoints that each includes one or more endpoints configured to impart a service and an endpoint that includes Flash storage; packets received from an external network are propagated through defined sequences of endpoints; services are imparted to a received packet by endpoints that receive it in the course of its propagation.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: June 4, 2019
    Assignee: Sanmina Corporation
    Inventors: Jon Livesey, Sharad Mehrotra, Thomas Gourley, Julian Ratcliffe, Jack Mills
  • Patent number: 10298447
    Abstract: Certain aspects direct to systems and methods for device or vendor independent network switch management on a management controller. The management controller is communicatively connected to a network switch through a Simple Network Management Protocol (SNMP) interface. The management controller receives parsed information of a management information base (MIB) file corresponding to the network switch, and establishes a communication between the management controller and the network switch through the SNMP interface based on the parsed information of the MIB file, in which the management controller functions as a client and the network switch functions as a server of the communication. Then the management controller receives an input to manage and configure the network switch, and manages and configures the network switch via the communication through the SNMP interface based on the input and the parsed information of the MIB file.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 21, 2019
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Samvinesh Christopher, Varadachari Sudan Ayanam
  • Patent number: 10289596
    Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: May 14, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui Chen, Kuen-Long Chang, Su-Chueh Lo, Chun-Yu Liao
  • Patent number: 10275389
    Abstract: A module comprising a USB Type-C receptacle, a USB Type-C plug and a logic unit is disclosed. A power pin of the receptacle is connected with another power pin of the plug via a switch. A CC pin of the receptacle is connected to ground through a pull-down resistance. Another CC pin of the plug is connected to the logic unit through a pull-up resistance. The module connects with a power source device being a power sink-role in order to receive a source capability of the power source device, then turns on the switch and transforms itself to a power source-role. The module connects to a DRP device afterward being the power source-role to act for the power source device and perform a USB PD communication with the DRP device.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 30, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tien-He Chen, Che-Min Chen
  • Patent number: 10261924
    Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Hemant Nautiyal, Rajan Kapoor, Arvind Kaushik, Puneet Khandelwal
  • Patent number: 10255215
    Abstract: Enhanced data storage devices in various form factors are discussed herein. In one example, a storage drive includes a plurality of storage devices configured to store and retrieve data responsive to operations received over Peripheral Component Interconnect Express (PCIe) interfaces, a PCIe switch circuit communicatively coupled to the PCIe interfaces of the storage devices and configured to receive over a host connector the operations issued by a host system and transfer the storage operations for ones of the storage devices over associated ones of the PCIe interfaces. The storage drive includes holdup circuitry configured to provide holdup power the storage devices. The storage drive includes a first circuit board assembly comprising three storage device connectors that couple to corresponding storage devices, and a second circuit board assembly comprising a further storage device connector that couples to a further storage device.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: April 9, 2019
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Brenden Michael Rust, Christopher R. Long, Andrew Rudolph Heyd, Sumit Puri, Bryan Schramm, Seth Walsh
  • Patent number: 10235313
    Abstract: A connecting circuitry is disclosed. The connecting circuitry is coupled to a storage device, a first motherboard and a second motherboard, and controlled by a first control signal and a second control signal to switch over to a first mode, to a second mode and to a third mode. The connecting circuitry includes a first exchanging unit; a second exchanging unit; and a first multiplexing unit, electrical connected to the first exchanging unit and the second exchanging unit; wherein the first mode is the storage device being only accessed by the first motherboard, the second mode is the storage device being only accessed by the second motherboard, and the third mode is the storage device being accessed by both the first motherboard and the second motherboard.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: March 19, 2019
    Assignee: Wistron Corporation
    Inventors: Syu-Siang Lee, Ming-Chun Lee, Zh-Wei Zhang
  • Patent number: 10228968
    Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. For each virtual NID there is a block in a memory of a transactional memory on the NID. This block stores configuration information that configures the corresponding virtual NID. The NID also has a single managing processor that monitors configuration of the plurality of virtual NIDs. If there is a write into the memory space where the configuration information for the virtual NIDs is stored, then the transactional memory detects this write and in response sends an alert to the managing processor. The size and location of the memory space in the memory for which write alerts are to be generated is programmable. The content and destination of the alert is also programmable.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 12, 2019
    Assignee: Netronome Systems, Inc.
    Inventors: Gavin J. Stark, Rolf Neugebauer
  • Patent number: 10210113
    Abstract: A diagnostic testing utility is used to perform online path diagnostic tests to troubleshoot components in a path that contribute to performance degradations and check application level data integrity, while traffic is allowed to flow as normal. To perform the diagnostic tests, two HBA or CNA ports at each end of a path are identified and used to send test frames to perform the diagnostic tests. The entire diagnostic procedure is performed without taking any ports or servers offline.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 19, 2019
    Assignee: BROCADE COMMUNICATIONS SYSTEMS LLC
    Inventors: Krishnakumar Gowravaram, Ramkumar Vadivelu, Varghese Kallarackal, Vinodh Ravindran
  • Patent number: 10203907
    Abstract: The present disclosure relates to a method and apparatus for measuring performance of a storage system. The method comprises: causing one or more entities to execute a task set comprising multiple tasks, each of the multiple tasks being used for accessing the storage system; obtaining an indicator set of the storage system based on a result of the execution, the indicator set comprising one or more indicators for indicating performance of the storage system; and adjusting the task set based on the indicator set, for subsequent execution by the one or more entities. The method can be executed iteratively. By means of the present invention, workloads for the next round's execution can be intelligently improved according to execution results after each round's execution of workloads, so that performance of the storage system can be obtained more pertinently and efficiently so as to better utilize the storage system.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: February 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ziye Yang, Chenhui Fan, Ping Chen, Xi Chen, Hailan Chen
  • Patent number: 10198185
    Abstract: A computing system includes: a gateway block configured to generate a modified operation for communicating a request operation issued by a host device to access a storage device; and wherein the gateway block includes: a conversion block configured to generate a converted interface for converting an interaction interface included in the request operation to the interaction interface executable by the storage device, and a translation block, coupled to the conversion block, configured to generate a translated representation for translating an object representation included in the request operation to the object representation utilized in the storage device.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongchul Park, Yang Seok Ki
  • Patent number: 10198388
    Abstract: A data storage system and associated method of using may generally have at least a data storage device that has independent first and second interfaces respectively connecting the data storage device to a host controller and an auxiliary controller. The auxiliary controller can be configured to provide system information to the data storage device prior to a synchronized connection being established between the data storage device and the host controller.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: February 5, 2019
    Assignee: Seagate Technology LLC
    Inventor: Michael Howard Miller
  • Patent number: 10162779
    Abstract: A computing device may include a universal serial bus (USB) port, a port controller, and a first port multiplexer. The port controller may determine that a connector of a cable has been connected to the port of the computing device and determine that the cable includes a second port multiplexer. The port controller may send a first instruction to the first port multiplexer to select a single-ended signaling configuration and send a second instruction to the second port multiplexer to select the single-ended signaling configuration. In the single-ended configuration, the first port multiplexer may receive a set of differential signals, convert the set of differential signals to a corresponding set of single-ended signals, and output the set of single-ended signals to the port.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Dell Products L.P.
    Inventor: Arnold Thomas Schnell
  • Patent number: 10157158
    Abstract: A system includes a first electronic control unit (ECU) processor configured to function as a scheduler, connected to a bus on a controller area network. The processor is also configured to receive an availability notification, indicating ECU available processing power, from a second ECU connected to the bus. The processor is further configured to instruct the second ECU to become the scheduler, responsive to a determination that the ECU available processing power is greater than processing power available locally on the first ECU.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 18, 2018
    Assignee: Ford Global Technologies, LLC
    Inventors: Matthew Charles Cross, Joann Xing, Peter Treman, Chad Everet Esselink
  • Patent number: 10127163
    Abstract: A control device for controlling a safety device which can be connected to a master assembly by means of an IO link is characterized in that a safety protocol can be transmitted via an IO link connection.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: November 13, 2018
    Assignee: Balluff GmbH
    Inventor: Albert Feinaeugle
  • Patent number: 10114790
    Abstract: An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM_OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 30, 2018
    Assignee: Microsemi Solutions (U.S.), Inc.
    Inventors: Kiran Hanchinal, Kuan Hua Tan, Richard David Sodke, Gregory Arthur Tabor
  • Patent number: 10101734
    Abstract: An Enterprise Resource Planning (ERP) gateway is provided for routing of ERP messages to Manufacturing Execution System (MES) applications. The gateway can receive a message from an ERP system via a manufacturing services bus specifying a business objective requiring action at a control level of an enterprise. The received message can be routed to a selected MES application capable of carrying out the business objective based on attributes within the message. Message routing can be based on location tags contained in the message. The message can also be routed to a selected subset of MES applications based on an analysis of respective capabilities and control contexts of the MES applications. Messages can be routed between the ERP system and the MES applications via the manufacturing services bus, which can manage protocol transformations for a heterogeneous set of applications.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 16, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: David Cooper, Kevin Chao, Keith Chambers, Richard Sze, Crisler Moor, Brandon E. Henning, Suryanarayana Murthy Bobba