Abstract: A memory system implements a plurality of virtual address modification policies and optionally a plurality of cache eviction policies. Virtual addresses are optionally, selectively, and/or conditionally modified by the memory system in accordance with a plurality of virtual address modification policies. The virtual address modification policies include no modification, modification according to two-dimensional Morton ordering, and modification according to three-dimensional Morton ordering. For example, in response to a reference to a particular virtual address, the particular virtual address is modified according to two-dimensional Morton ordering so that at least two elements in a same column and distinct respective rows of a two-dimensional data structure are loaded into a same cache line and/or are referenced via a same page table entry.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: A system and method for performing coarse-grained deduplication of volume regions. A storage controller detects that a first region of a first volume is identical to a second region of a second volume, wherein the first volume points to a first medium and the second volume points to a second medium. In response to detecting the identical regions, the storage controller stores an indication that the first range of the first medium underlies the second range of the second medium. Also in response to detecting the identical regions, the mappings associated with the second range of the second medium are invalidated.

Abstract: A method of providing access to first data stored at a first device to a second device, the first device storing the first data in a memory accessible to said second device. The method comprises, at a control element distinct from each of said first and second devices accessing the stored first data in said memory accessible to said second device before said first data is accessed in said memory accessible to said second device by said second device.

Abstract: In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3).

Abstract: An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB (universal serial bus) port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM (programmable read only memory), and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS (basic input/output system), may be modified or replaced.

Abstract: In accordance with methods of the present disclosure, a system may include a switch and a management controller communicatively coupled to the switch. The switch may be configured to route input/output communications between a processor and a device. The management controller may be configured to, based on a measured bandwidth of communications of a communication link between the switch and the device, dynamically control at least one of a link width and a per-lane link speed of the communication link.

Abstract: A method for providing virtualization of information handling resources includes accessing a information handling system and a information handling resource, accessing a first virtual function configured to cause virtualized access to the information handling resource through the interface, accessing a second virtual function configured to cause virtualized access to the information handling resource through the interface, and selectively mapping the first virtual function and the second virtual function to information handling systems of the system. The selective mapping includes preventing the first virtual function and the second virtual function from both being mapped to the same information handling system.

Abstract: A cubesat communications system includes an on-board computer implemented on a hardware platform. The on-board computer may include a system on module having a processor and a memory storing “boot” information. The on-board computer may also include a plurality of hardware interfaces implemented on the hardware platform to facilitate communication between the processor and a plurality of peripherals external to the on-board computer. The on-board computer may have a backplane having a plurality of connectors connecting the processor to the peripherals.

Abstract: One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes transmitting to GPU graphics processing commands received from a graphics application, where the graphics processing commands are configured to cause the GPU to render a first set of graphics data, determining that graphics data should be collected for transmission to the secondary computer, conveying to the GPU that the first set of graphics data should be stored in a first buffer within a frame buffer memory, transmitting to the GPU graphics processing commands received from a process application executing on the primary computer, where the graphics processing commands are configured to cause the GPU to perform operations on the first set of graphics data to generate a second set of graphics data, and transmitting the second set of graphics data to the secondary computer.

Abstract: A method is described for serial data transmission in a bus system having at least two participating data processing units, the data processing units exchanging messages via the bus, the sent messages having a logical structure in accordance with CAN standard ISO 11898-1. When a first changeover condition is present, then, deviating from CAN, the data field of the messages can include more than eight bytes, the values of the data length code being interpreted, given the presence of the first changeover condition to determine the size of the data field. For forwarding data between the data field and the application software, at least one buffer memory is provided, and, if the size of the data field differs from the size of the buffer memory used, the forwarded quantity of data is adapted at least corresponding to the difference in size between the data field and the buffer memory.

Abstract: Managing a networked storage system having a host operable to connect through a network fabric to storage apparatus comprises: a configuration component for inputting a configuration change into the networked storage system responsive to change instructions; a monitoring component operable in communication with the host and the network fabric to monitor I/O activity associated with elements of the networked storage system; an activity data storage component responsive to the monitoring component for storing a record of a monitored I/O activity; an analysis component, responsive to the configuration component for inputting configuration changes, for analyzing the record of a monitored I/O activity for a recent activity; and an alert component, responsive to the analysis component detecting a recent activity, for alerting the configuration component.

Abstract: An aspect provides a method, including: ascertaining, at a first device, a request to transfer media data to another device; determining, at the first device, a plurality of connected devices for potential transfer of media data corresponding to the request; providing, at the first device, a disambiguation cue to a user; ascertaining via the disambiguation cue a target device from the plurality of connected devices for transfer of the media data; and transferring the media data to the target device. Other aspects are described and claimed.

Abstract: The present invention provides a mechanism for fast routing of data in a Storage Area Network. A protocol interface module (PIM) interfaces with outside networks and the storage devices, such as over fiber channel (FC). The PIM encapsulates received data into a streaming protocol, enabling storage processors to direct data to/from the appropriate physical disk in a similar manner to the directing of network messages over the Internet or other network.

Abstract: Aspects disclosed in the detailed description include high-frequency signal observations in electronic systems. In this regard, a high-frequency signal observation circuit is provided in an electronic system to enable high-frequency signal observations. In one aspect, the high-frequency signal observation circuit comprises an observation signal selection circuit. The observation signal selection circuit is programmably controlled to select an observation signal among a plurality of electronic input signals (e.g., control signals) received from the electronic system. In another aspect, the high-frequency signal observation circuit is configured to utilize a bypass data path, which is routed around serializer/deserializer (SerDes) logic in the electronic system, to output the observation signal for observation. By programmably selecting the observation signal and outputting the observation signal via the bypass data path, it is possible to examine accurately any high-frequency signal (e.g.

Abstract: Providing a snapshot of a physical memory region as of a specified time includes: sending, from a first processor to a second processor, a request to generate a snapshot of the physical memory region as of the specified time; and generating, using the second processor, the snapshot of the physical memory region based at least in part on a known state of the physical memory region and log information about update activity of the physical memory region.

Abstract: Systems and methods for negotiating control of a shared audio or visual resource are disclosed. A request for control of a shared audio or visual resource is received at an arbiter. The arbiter maintains existing state information for ownership of the shared audio or visual resource and ownership transition conditions of the shared audio or visual resource. The request is received from one of a process executing on an embedded system and a process executing on a mobile computing device. New state information regarding ownership of the shared audio or visual resource is determined based at least in part on the request for control and the ownership transition conditions. The new state information indicates which of the processes controls output of the shared audio or visual resource.

Abstract: Systems, apparatuses, computer readable media, and methods for creating, exporting, sharing, and installing graphics functional blocks are described herein. In one embodiment, a selection is received from a graphical user interface (GUI) for one or more patches of multiple linked patches representing a graphics composition. In response to the selection, a dependency analysis is performed to determine one or more related patches that have a dependency relationship with the selected patches. Based on the dependency analysis, source code associated with the selected patches and the related patches is extracted without extracting source code of unselected and unrelated patches. Thereafter, the selected patches, the related patches, and the extracted source code are exported into a composition file to be shared with another user. Other methods and apparatuses are also described.

Abstract: A substrate processing system includes a main control unit having a configuration file in which ID information and detail information about devices for processing a substrate is recorded, the detail information includes information needed for controlling the devices, and a module controller having a list file obtained by converting the configuration file into a readable form, the module controller controlling the devices described in the list file on the basis of instructions from the main control unit. The module controller automatically adds, to the list file, ID information and detail information about a new device newly connected to the module controller to establish a condition under which the new device can be controlled.

Abstract: Example methods, apparatus, and articles of manufacture to control generation of memory access requests in processor systems are disclosed. A disclosed example method involves determining at a memory controller whether a memory access queue depth for a memory reference is greater than a first threshold. When the memory access queue depth for the memory reference is greater than the first threshold, an indication is sent to control generation of memory access requests corresponding to the memory reference.