Patents Examined by Colleen E Snow
  • Patent number: 11978625
    Abstract: Embodiments of the disclosure include methods of forming a film comprising conformally depositing a first film on a substrate; treating the first film with a first plasma to form a second film; treating the second film with a second plasma to form a third film; and selectively removing the first film, a portion of the second film, and the third film.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 7, 2024
    Assignee: Applied Materials, Inc.
    Inventor: Joseph AuBuchon
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11963377
    Abstract: A light-emitting diode display including a substrate having a driving circuitry and a plurality of light emitting diode structures disposed on the substrate. Each light-emitting diode structure has a light emitting diode with a light emission zone having a planar portion, and a pigmentless light extraction layer of a UV-cured ink disposed over the light-emitting diode. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion, and the index of refraction of the light extraction layer decreases with distance from the planar portion.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: April 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Gang Yu, Chung-Chia Chen, Wan-Yu Lin, Hyunsung Bang, Lisong Xu, Byung Sung Kwak, Robert Jan Visser
  • Patent number: 11955383
    Abstract: A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.
    Type: Grant
    Filed: November 7, 2021
    Date of Patent: April 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie Liu, Bin Yang, Zhan Ying
  • Patent number: 11937438
    Abstract: An organic field-effect transistor and a fabrication method therefor, including: providing a gate; depositing polymer material onto the gate to form a dielectric layer; performing supercritical fluids treatment on the gate having the dielectric layer deposited; depositing organic semiconductor layer material on the dielectric layer having been processed, to form an organic semiconductor layer; depositing electrode layer material on the organic semiconductor layer and forming an electrode layer. The dielectric properties of the dielectric layer after adopting the supercritical fluids treatment have been significantly improved. While the hysteresis effect of the dielectric layers in the OFET devices has been basically eliminated, the sub-threshold slope of the OFET is also significantly reduced, the carrier mobility is effectively improved. Additionally, an OFET switching rate after being processed is improved, and, by connecting the LEDs in series, the switching rate of the LED is increased.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: March 19, 2024
    Assignee: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL
    Inventors: Hong Meng, Yuhao Shi, Xinwei Wang, Lin Ai
  • Patent number: 11929389
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
  • Patent number: 11901427
    Abstract: In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 13, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Junjing Bao
  • Patent number: 11869772
    Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 9, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Denis Monnier, Olivier Gonnard
  • Patent number: 11862685
    Abstract: The wafer having a retardation distribution measured with a light having a wavelength of 520 nm, wherein an average value of the retardation is 38 nm or less, wherein the wafer comprises a micropipe, and wherein a density of the micropipe is 1.5/cm2 or less, is disclosed.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 2, 2024
    Assignee: SENIC INC.
    Inventors: Jong Hwi Park, Kap-Ryeol Ku, Jung-Gyu Kim, Jung Woo Choi, Myung-Ok Kyun
  • Patent number: 11856795
    Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor device. The semiconductor includes a transistor, a first metallization layer over the transistor, a phase change material over the first metallization layer, a second metallization layer over the phase change material, a heater between the first metallization layer and the second metallization layer and in contact with the phase change material, the heater including a heat insulation shell having a first heat conductivity, wherein the heat insulation shell includes a superlattice structure, and a heat conducting core contacting the heat insulation shell and having a second heat conductivity different from the first heat conductivity.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 11854961
    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 26, 2023
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Tao-Chih Chang, Yu-Min Lin, Sheng-Tsai Wu
  • Patent number: 11849637
    Abstract: The present disclosure provides a nitrogen-containing compound, an electronic component comprising same, and an electronic device, and belongs to the technical field of organic electroluminescence. In the compound of the present disclosure, the nitrogen-containing compound is more suitable for being used as an electronic-type host material in the mixed host of the luminescence layer of an organic electroluminescent device, and is especially suitable for being used as an electronic-type host material in a green light device. When the nitrogen-containing compound of the present disclosure is used as a luminescence layer material of the organic electroluminescent device, the electron transporting performance of the device is effectively improved, the luminescence efficiency of the device is improved, and the service life of the device is prolonged.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: December 19, 2023
    Assignee: Shaanxi Lighte Optoelectronics Material Co., Ltd.
    Inventors: Tiantian Ma, Yan Zang, Peng Nan
  • Patent number: 11843027
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes laminating a thermally decomposable organic material on a substrate by supplying a material gas into a container in which the substrate having a first recess and a second recess, which has a wider width than a width of the first recess, are formed, fluidizing the organic material laminated on the substrate by heating the substrate to a first temperature, and removing the organic material laminated in the second recess.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 12, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Syuji Nozawa
  • Patent number: 11837662
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
  • Patent number: 11791256
    Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: October 17, 2023
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 11764109
    Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 19, 2023
    Assignee: AMS AG
    Inventors: Jochen Kraft, Georg Parteder, Stefan Jessenig, Franz Schrank, Jörg Siegert
  • Patent number: 11732188
    Abstract: The present invention relates to a composition comprising a semiconducting light emitting nanoparticle.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 22, 2023
    Assignee: MERCK PATENT GMBH
    Inventors: Yuki Hirayama, Tomohisa Goto, Tadashi Kishimoto, Masayoshi Suzuki, Teruaki Suzuki
  • Patent number: 11688769
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack. The semiconductor device structure also includes a cap element over the source/drain structure. The cap element has a first top plane, and the source/drain structure has a second top plane. The first top plane of the cap element is wider than the second top plane of the source/drain structure. A surface orientation of the first top plane of the cap element and a surface orientation of a side surface of the cap element are different from each other. The surface orientation of the first top plane of the cap element is {311}.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Huang Wu, Jian-Shian Chen
  • Patent number: 11690274
    Abstract: A display apparatus may include: a cover member comprising a hole area; a light shielding layer, an adhesive layer and a display layer that are disposed under the cover member; a first opening provided at the adhesive layer and the display layer corresponding to the hole area; a camera module inserted into the first opening; and an intermediate member disposed between the hole area and the camera module.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: June 27, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Jaeyul Kim, Jasung Choi
  • Patent number: 11688838
    Abstract: A method of manufacturing a light emitting device includes: providing two light emitting elements disposed on a first surface of a light transmissive member; disposing a light guide member covering a part of the first surface of the light transmissive member, and lateral surfaces of the two light emitting elements; disposing a light reflective member covering the two light emitting elements, a second surface of the light transmissive member, and the light guide member, the second surface of the light transmissive member being opposite to the first surface; and cutting the light reflective member and/or the light transmissive member between the two light emitting elements.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 27, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Tadao Hayashi