Abstract: An organic light-emitting diode (OLED) structure includes a stack of OLED layers that includes a light emission zone having a planar portion, and a light extraction layer formed of a UV-cured ink disposed over the light emission zone of the stack of OLED layers. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same and a display device. The display substrate includes a base substrate, first wires on a side of the base substrate, a first barrier layer on the side of the base substrate; and a second wire on a side of the first barrier layer distal to the base substrate, where the first wires and the second wire being adjacent to and spaced apart from each other.

Abstract: The present invention relates to an apparatus and a method for manufacturing a light-emitting diode (LED) module and, more particularly, to an apparatus and a method for manufacturing a light-emitting diode module, which are capable of manufacturing a light emitting diode module on which a plurality of light-emitting diodes are mounted with an improved bonding speed and high accuracy by manufacturing the light-emitting diode module by simultaneously transferring the plurality of light emitting diodes onto a substrate by using a multi-eject pin or a multi-collet.

Abstract: The wafer having a retardation distribution measured with a light having a wavelength of 520 nm, wherein an average value of the retardation is 38 nm or less, wherein the wafer comprises a micropipe, and wherein a density of the micropipe is 1.5/cm2 or less, is disclosed.

Abstract: A semiconductor structure includes a first conductive line and a second conductive line in a first dielectric layer, and a third conductive line in a second dielectric layer overlying the first dielectric layer. The first conductive line and the second conductive line each extend along a first direction. The third conductive line extends along a second direction different from the first direction and above at least the second conductive line. The semiconductor structure further includes a via in the second dielectric layer and electrically connecting the second conductive line and the third conductive line. The via lands on a portion of the second conductive line. The semiconductor structure further includes a dielectric cap over the first conductive line. A bottom surface of the dielectric cap is below a top surface of the first dielectric layer.

Abstract: The image display device sealing material contains a resin component and a curing agent, wherein the resin component contains biphenyl skeleton-containing epoxy resin having a weight-average molecular weight of 200 or more and 100,000 or less, alicyclic skeleton-containing epoxy resin having a weight-average molecular weight of 180 or more and 790 or less, and styrene oligomer having a weight-average molecular weight of 750 or more and 4000 or less.

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

Abstract: A thin-film encapsulation structure includes a number of inorganic film layers and at least one organic film layer laminated alternately at one side of an organic light-emitting diode. The number of inorganic film layers include N inorganic film layers including first to N-th inorganic film layers arranged sequentially from inside to outside, N?2. At least the first inorganic film layer has a refractive index increasing gradually from inside to outside.

Abstract: [Object] To provide a display apparatus that makes it possible to improve visibility. [Solution] A display apparatus according to an embodiment of the present disclosure includes: a display body device including a plurality of pixels, the plurality of pixels each including a plurality of light-emitting elements as light source elements; and an irregular structure formed on a front surface of the display body device.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.

Abstract: A mounting substrate has a patterned metal layer defining a plurality of top metal bond pads for bonding to bottom metal bond pads of LED dies. A solder mask layer is formed over the mounting substrate, where the mask has openings that expose the top metal bond pads and protects metal traces on the substrate. The mask layer is a highly reflective white paint. The exposed top metal bond pads are then wetted with solder. The LED dies' bottom metal bond pads are then soldered to the exposed top metal bond pads, such that the mask layer surrounds each LED die to reflect light. A reflective ring is affixed to the substrate to surround the LED dies. A viscous phosphor material then partially fills the ring and is cured. All downward light by the LED dies and phosphor is reflected upward by the ring and solder mask layer.

Abstract: [Object] To provide a display apparatus that makes it possible to improve visibility. [Solution] A display apparatus according to an embodiment of the present disclosure includes: a display body device including a plurality of pixels, the plurality of pixels each including a plurality of light-emitting elements as light source elements; and an irregular structure formed on a front surface of the display body device.

Abstract: Die handling systems and methods of use for preparing or processing dies from multiple types of pre-expanded wafer materials. The die handling systems are configured in a modular fashion, allowing for concurrent processes to expand the wafers, process the wafers, extract the dies, and inspect the extracted dies without forcing one of the processes of the system to remain idle. Embodiments of the wafer handler module include a mechanism, such as an expander capable of stretching or expanding wafers having one or more different sizes to a pre-expanded state without interrupting the die handler. The pre-expanded wafers are stored as a proprietary cartridge and delivered to the die handler, where a pick head of the die handler removes each die of the pre-expanded wafer and delivers the extracted dies to subsequent machinery, such as a pick and place machine, for further processing.

Abstract: A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 1×1021 cm?3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.

Abstract: A display device may include a substrate, a first layer on the substrate, the first layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a second layer on the first layer, an active pattern on the second layer, the active pattern overlapping only the first portion of the first layer, a gate electrode on the active pattern, a source electrode and a drain electrode on the gate electrode and connected to the active pattern, a first electrode connected to one of the source electrode and the drain electrode, a pixel defining layer on the first electrode, the pixel defining layer having an opening portion exposing at least a portion of the first electrode, an emission layer in the opening portion on the first electrode, and a second electrode on the emission layer.

Abstract: Disclosed herein are optical stacks that are stable to light exposure by incorporating one or more UV-blocking layers.

Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

Abstract: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.

Abstract: A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.