Abstract: Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extract a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent scaling value. The residuary subset bitfield value is part of a range of contiguous bits that is associated with upper and lower boundary bit-position values that are part of the compound exponent scaling value. The methods and apparatus determine the remainder value based on the residuary subset bitfield value.

Abstract: Methods, devices and a software product for generating a sinusoidal signal of a desired frequency at a desired sampling rate. If the frequency is higher than the upper limit, a coefficient is determined as a function of the sampling rate and a sample of the first output sample sequence is determined as a linear combination of the coefficient and two previous output samples. The first output sample sequence is decimated by the sampling rate. If the frequency is lower than the lower limit, the coefficient is determined as a function of the sampling rate and the sample of the first output sample sequence is determined as a linear combination of the coefficient and two previous output samples. The first output sample sequence is multiplied so as to generate a second output sample sequence. The second output sample sequence is decimated by the sampling rate.

Abstract: A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment supporting a union declaration functionality and a left shift functionality. Accordingly, an input receives an exponent value, and a bias application module biases the exponent value based on a selected precision of a floating point data type. Also, a storage module stores the exponent value in a storage variable having a size determined based on the selected precision. Further, a left shift application module shifts the exponent value left by a number of bits determined based on the selected precision. Finally, an output returns the storage variable as the floating point data type having the selected precision.

Abstract: An electronic dB-to-linear gain conversion system (10). The system comprises an input (12) for receiving a gain index signal (GI) representing a desired dB value. The desired dB value is selected from a set having an integer number S of dB values. The system also comprises a storage circuit (16) for storing an integer number V of linear gain values and circuitry for producing a linear gain signal (LG) in response to the gain index signal and to one of the V linear gain values. In the preferred embodiment, V is less than S.

Abstract: A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

Abstract: A method for representation, interpolation and/or compression of data includes identifying a two-dimensional interpolation function s(z) based on a sampling function a(z). A Cauchy integral theorem is applicable for the interpolation function s(z). The interpolation function s(z) is used for the representation, interpolation and/or compression of the data.

Abstract: The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via “all-to-all” distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates eff

Abstract: A method, computer program product and data processing apparatus for filtering data, in particular for use in deblocking filters. The method comprising applying a plurality of m filter coefficients which each have a value which is a negative power of two and which sum to one, to a plurality of m input data items to produce a filtered output data item, by performing a sequence of averaging calculations comprising averaging input data items to which a smallest filter coefficient is to be applied to produce first averaged data and averaging the first averaged data with other averaged input data or with input data items to which larger filter coefficients are to be applied the plurality of m filter coefficients being applied to the plurality of m input data items via a sequence of averaging calculations such that a data width of any calculated data does not exceed that of the input data being averaged.

Abstract: A random number generator includes a flip-flop, and a pair of independent free-running oscillators having a respective set of 4 switches controlled with a non-inverted and inverted output of the flip-flop. An output from each of the oscillators is fed back to their respective input via a delay device. The pair of oscillators each has a feedback loop switch, and a pair of cross gate switches, each of which respectively connects an input signal of one oscillator to an output of another oscillator of the pair of oscillators. When the feedback loop switches are open and the cross gate switches are closed, the pair of oscillators forming a flip-flop with positive feedback resolves to a logic state that in a metastable way, producing an unpredictable (random) logic signal.

Abstract: A multiplier circuit is disclosed for multiplying a multiplicand by a multiplier. The multiplier circuit includes a partial product generator and a partial product adder. The partial product generator includes a first input to receive a multiplicand; a second input to receive a multiplier; partial product generation means for producing a plurality of partial products based on the multiplicand and the multiplier; and an output coupled to the partial product generation means to provide the plurality of partial products. The partial product adder includes an input coupled to the output of the partial product generator; a plurality of adders to add the plurality of partial products to produce a final product, the plurality of adders comprising a plurality of compressors having substantially the same width; and an output coupled to the plurality of adders to provide the final product.

Abstract: A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible.

Abstract: Method and apparatus for providing random bits are described. In one embodiment, random bits are provided by storing a succession of random bits in a buffer. A quantity of bits is selected from the buffer at a source location and used as a basis of a new quantity of random bits. The content of the buffer is altered and the source location is advanced to the next position in the buffer. The source location is placed at the beginning of the buffer plus an offset when the next location is beyond the limit of the buffer.

Abstract: The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of 4-bits each, computes an intermediate sum vector and carry vector without considering the input carry bit, and also computes propagation and generate functions for each 4-bit group. The second stage is a carry look ahead circuit which computes all carries from the input carry, and the propagate and generate functions of the 4-bit groups from the first stage. The third stage adjusts the intermediate sum vector with pre-correction factors which depend upon the input carry and the carries generated from the second stage and the carry vectors from the first stage.

Abstract: One embodiment of the present invention provides a system that solves an overdetermined system of interval linear equations. During operation, the system receives a representation of the overdetermined system of interval linear equations Ax=b, wherein A is a matrix with m rows corresponding to m equations, and n columns corresponding to n variables, and wherein x includes n variable components, b includes m scalar components, and m>n. Next, the system performs a Gaussian Elimination operation to transform Ax=b into the form [ T W ] ? x = [ u v ] , wherein T is a square upper triangular matrix of order n, u is a vector with n components, v is a vector with m?n components, and W is a matrix with m?n rows and n columns, wherein W is zero except in the last column, which is represented as a column vector z with m?n components. Next, the system performs an interval intersection operation based on the equations zixn=vi (i=1, . . . , m?n) and Tnnx=un to solve for xn.

Abstract: The present invention relates to a novel matrix-valued transform framework to process digital signals. According to one aspect of the invention, matrix-valued methods and apparatus are described to transform a vector-valued discrete-time data sequence from time-domain into frequency-domain. In another aspect, matrix-valued methods and apparatus are described to transform a vector-valued data sequence from frequency-domain into time-domain. Furthermore, the new framework disclosed in this invention also provides a plurality of methods and apparatus for basic signal processing functions and operations of a matrix-valued communication system. These functions and operations include but are not limited to matrix-valued fast Fourier transformation, matrix-valued linear and circular convolution, matrix-valued correlation, matrix-valued multiplexing and de-multiplexing, and matrix-valued data coding and decoding.

Abstract: The present invention relates to a method and system for providing a variable width, at least six-way addition instruction in a processor. The method includes decoding an instruction as a variable width, at least six-way addition instruction, where the variable width, at least six-way addition instruction includes a plurality of operands. The method also includes adding the plurality of operands to obtain a plurality of sums. The method further includes outputting the plurality of sums and optionally storing carry results from the adding operation.

Abstract: A random number source includes a ring oscillator generating an internal clock signal having random phase noise, and a first linear feedback shift register connected to the ring oscillator. A counter is connected to a first tap of the first linear feedback shift register for generating a count signal. A feedback bit controller is connected to a second tap of the first linear feedback shift register for generating a random feedback bit for a time based upon the count signal. A second linear feedback shift register is connected to the feedback bit controller for generating a random number based upon the random feedback bit.

Abstract: Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-integer value. The multiplier value is determined by extracting information from a first portion of a bitfield based on the scaled-integer value. The scale value is determined by extracting information from a second portion of the bitfield based on the scaled-integer value. The first and second portions of the bitfield are configurable to include signed integer values. The example method then performs an arithmetic operation based on the multiplier value and the scale value.

Abstract: A method and apparatus for fast digital filtering that requires only filter stages of first and second order. A desired rational filter transfer function is represented as a sum of first and second order intermediate transfer functions. A time dependent input signal is first fed in parallel into a plurality of first and second order intermediate recursive filter stages. Then, the outputs of the intermediate filter stages are summed up to an output filter signal that corresponds to the desired rational filter transfer function. The method and apparatus reduces the amount of calculational effort to the order of O(N), where N denotes the number of sampling points in the time domain, because the digital filtering is based on a discrete recursive convolution in the time domain.

Abstract: A calculation speed of division carried out in a computer is increased. Partitioning means partitions a dividend y that is a 32-bit digital datum at every 8 bits from the least significant bit to generate four bit blocks y(1) to y(4). For the respective bit blocks, table reference means finds solutions z(1) to z(4) obtained by dividing, by a divisor x, values expressed by replacing the bits other than the bits in each bit block with 0, while referring to tables (1) to (4) stored in storage means. Addition means adds all the solutions z(1) to z(4) to find the solution z.