Abstract: A power of a square matrix is determined in a time approximately proportional to the upper integer of the base-2 logarithm of the order of the matrix. A preferred embodiment uses two types of look-up tables and two multipliers for a matrix of 15×15, and is applied to a pseudorandom noise (PN) sequence phase correlation or state jumping circuit. An exact state of a PN code can be determined or calculated from applying an appropriate offset value into a control circuit. The control circuit can produce a PN sequence state from the offset value and typically does so within one system clock period regardless of the amount of the offset. Once the exact state is determined, it is loaded into a state generator or linear sequence shift register (LSSR) for generating a subsequent stream of bits or symbols of the PN code. The PN generator system may include state computing logic, a maximum length PN generator, a zero insertion circuit and a zero insertion skipping circuit.

Abstract: A physical random number generator has a bi-stable latch that operates to generate a random number bit in response to a reception of one or more voltage input signals and a clock signal. A voltage source provides the voltage input signal(s) for provoking the bi-stable latch into a metastable state. A clock provides the clock signal for triggering the bi-stable latch. When triggered, the bi-stable latch latches the random number bit as a function of its metastable state provoked by the voltage input signal(s).

Abstract: The present invention provides apparatus, methods, and computer program products that can decrease the latency with which the coefficients of a function representative of signal are determined. Specifically, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, updates each of the coefficients of the function as each sample is received. As such, when the final sample is received, the apparatus, methods, and computer program products of the present invention need only update each coefficient with the contribution of the last sample prior to outputting the coefficients. As such, the latency from the time the last sample is received and the availability of the coefficients is decreased. To further decrease the latency, in one embodiment, the apparatus, methods, and computer program products of the present invention prestore either all or a portion of the possible values of the contribution of a sample to each coefficient, such that.

Abstract: An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection. This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.

Abstract: Methods and apparatus of signal processing are described. In a method according to one embodiment, a high-frequency region of a digital signal is detected. In response to the detecting, the high-frequency content of the digitized signal is increased in at least a portion of that region.

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: A waveform generator for use in IQ modulation in a wireless cellular device having an FM waveform generator (104) that is programmable to generate a desired FM frequency deviation; a digital accumulator (108, 110, 112) to provide phase generation. First and second look-up tables 114 and 116 use the 6 MSBs and the 6 LSBs of 12-bit digital accumulator values to look up phase-space values that are combined in complex multipliers (130, 140), which are re-used from other parts of the circuit. This provides the following advantage(s): Support of both FM and I/Q modulation techniques for constant envelope modulation; low cost implementation; and flexibility to address multimode systems.

Abstract: A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cin corresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically determining the carry Ci on the basis of the block carry Cin, and outputting the carry Ci to the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cin and is arranged on an output terminal side.

Abstract: A residue computing device on a Galois Field, for calculating a residue of a product of a multiplier factor and a multiplicand under a modulo, includes a gate for allowing the multiplier factor to pass therethrough when a leading bit of the multiplicand is 1, an adder for adding a temporary residue and a value obtained by the passage, a gate for allowing the modulo to pass therethrough when a leading bit of a summed value of the adder is 1, and a subtractor for subtracting the modulo from the summed value of the adder when the leading bit of the summed value is 1, wherein a process for setting a value obtained by shifting a subtracted value of the subtractor by one bit, as the temporary residue on the basis of the next clock is repeatedly performed for each clock to thereby calculate the residue.

Abstract: A novelty calculator and system of input and data manipulation for amusement. The preferred embodiment of the device contemplates a calculator having a body, keyboard for input of numerical data and functions, and a display similar to standard calculators. However, the calculator of the present invention is programmed to provide manipulated, erroneous responses or answers in response to data entered for a humorous or surprising reaction by an observer. The preferred embodiment of the present system includes function controls to provide predetermined manipulation of the of the data for amusement tailored to select themes.

Abstract: A Givens rotation computation technique is provided that makes use of polynomial approximations of an expression that contains a square root function. The polynomial approximation uses polynomial coefficients that are specifically adapted to respective ones of a number of subintervals within the range of possible values of the input variable of the expression. The technique may be used in data communications devices such as those in wireless local area networks. An example is the application of the Givens rotations technique in a decision feedback equalizer.

Abstract: A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.

Abstract: Channel coupling for an AC-3 encoder, using mixed precision computations and 16-bit coupling coefficient calculations for channels with 32-bit frequency coefficients.

Abstract: A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n?1?1.

Abstract: An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition circuit further includes a 4:3 compression adder for receiving each of the sparse carry-save fields of the four redundant binary numbers, and producing a second sum field therefrom. The addition circuit also includes a 3:2 compression adder for receiving the first sum field, the first carry field and the second sum field, and producing a third sum field and a second carry field therefrom. The third sum field and the second carry field are the final results from addition of the four redundant binary numbers.

Abstract: A method and system of accurately processing a discrete time input signal having a first clock rate into a discrete time output signal having a second clock rate is presented. The method includes delta filtering the input signal to produce an intermediate signal having the first clock rate and delta interpolating the intermediate signal to produce the output signal. Delta filtering includes calculating an input delta signal by subtracting an initial value from the input signal, generating a filtered delta signal, and adding the initial value to the filtered delta signal. Delta interpolating includes upsampling the intermediate signal to the second clock rate, calculating an upsampled intermediate delta signal by subtracting an initial value from the upsampled intermediate signal, filtering the intermediate delta signal, and adding the initial value to the filtered intermediate delta signal.

Abstract: In the method of generating a pseudo random number, pseudo random numbers equal to pseudo random numbers generated from a pseudo random number generation function indexed by orders of two are stored. Then, a pseudo random number is generated based on the stored pseudo random numbers.

Abstract: The present invention is a counter that takes advantage of the speed and implementation of the LFSR counter by utilizing separate digit counters, each digit counter having a period that is a relative prime to the other digit counter periods. The total period will be the product of all the digit counter periods. Since all digits count independently, there is no carry structure between the digits and hence no delay incurred by carry chains. The pseudorandom number counting sequence for each digit still occurs but is ameliorated by the fact that the digital periods are small and can readily be converted to decimal equivalents by table-lookup and residue lookup.

Abstract: The invention relates to an approximation of a DCT and a quantization which are to be applied subsequently to digital data for compression of this digital data. In order to improve the transform, it is proposed to simplify a predetermined transform matrix to require less operations when applied to digital data. In addition, elements of the simplified transform matrix constituting irrational numbers are approximated by rational numbers. These measures are compensated by extending a predetermined quantization to include the operations which were removed in the simplification of the predetermined transform matrix. The included operations are further adjusted to compensate for the approximation of elements of the simplified transform matrix by rational numbers. If the simplified transform matrix and the extended quantization are used as basis for implementation, a fast transform with a good resulting quality can be achieved.

Abstract: According to an embodiment of present invention, an algorithm for computing static pre-equalizer coefficients, comprises the steps of determining a length of algorithm iterations; calculating a feedforward coefficient vector associated with a feedforward equalizer; calculating a pre-equalizer coefficient vector associated with a pre-equalizer filter; and performing the steps of calculating for the length of the algorithm iterations; wherein a mean square of an error between an output sequence and a transmitted digital input sequence is minimized.