Abstract: An hand held implement which includes an integral preprogrammed electronic calculator. The implement is preset to perform one or more calculations which utilize known scientific formulas and mathematical relationships and which rely upon specific variables for which values are input by the user through the use of the various input command control devices and may be reused for further serial calculations. By preprogramming the implement with the related formulas for a given field of technology, the user may perform one or even a series of related and useful calculations without the need for any additional calculators, charts, tables or other printed materials. The surfaces on the implement may also be used for the imprinting of graphical or advertising material for the purpose of advertising or promotion.

Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0–XM?) with encoding coefficients (C0–CM?1), wherein each of (X0–XM?1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k?1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k?1). This is repeating for data bits (X1–XM?1) and corresponding coefficients (C1–CM?1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.

Abstract: The invention relates to an interpolation filter and to a method for filtering a digital input signal. The interpolation filter has an amplitude characteristic with a low-pass-shaped damping curve in the useful signal frequency range of the digital input signal. The group delay time of the interpolation filter is essentially constant in the useful signal frequency range and can be adjusted within a clock period of the equidistant digital signal.

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract: Aspects for performing a multiply-accumulate operation on floating point numbers in a single clock cycle are described. These aspects include mantissa logic for combining a mantissa portion of floating point inputs and exponent logic coupled to the mantissa logic. The exponent logic adjusts the combination of an exponent portion of the floating point inputs by a predetermined value to produce a shift amount and allows pipeline stages in the mantissa logic, wherein an unnormalized floating point result is produced from the mantissa logic on each clock cycle.

Abstract: One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the system receives an instruction to perform an arithmetic operation that involves manipulating floating-point values. If the arithmetic operation manipulates a floating-point value representing {+0}, the arithmetic operation is performed in a manner consistent with {+0} representing a set containing a single value “?0”, wherein “?0” is the limit of a sequence of values that approaches zero only from above. Similarly, if the arithmetic operation manipulates a floating-point value representing {?0}, the arithmetic operation is performed in a manner consistent with {?0} representing a set containing a single value “+0”, wherein “+0” is the limit of a sequence of values that approaches zero only from below.

Abstract: A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.

Abstract: The objective is to realize a numeric value search apparatus and numeric value search method capable of rapidly searching for a numeric value of a prescribed rank. The present invention is characterized in that it comprises the following: a storage unit which stores multiple pieces of digitized numeric value data; a resolution specifying means which specifies a frequency distribution resolution; a frequency distribution creation unit which determines the frequency distribution of numeric value data in the storage unit using the resolution specified by this resolution specifying means; and a computation unit which determines the numeric value range or numeric value with the prescribed rank from the frequency distribution determined by this frequency distribution creation unit; wherein the resolution specifying means increases the resolution specified to the frequency distribution creation unit in steps, based on the computation results of the computation unit.

Abstract: A waveform generator digitally synthesizes a waveform having a plurality of successive portions that can each be as short as one mono-cycle of the waveform, or a part of one mono-cycle. The waveform generator changes at least one of a frequency, a phase and an amplitude of the waveform between each successive pair of the portions thereof. A method includes digitally synthesizing a waveform having a plurality of successive portions that can each be as short as one mono-cycle of the waveform, or a part of one mono-cycle, including changing at least one of a frequency, a phase and an amplitude of the waveform between each successive pair of the portions thereof.

Abstract: A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First Stage Adder Circuit. The reduced spurious switching reduces the power dissipation of the Multiplier. The timing of the input signals is synchronized by means of the Latch Adders having a Latch that is an integral part of an Adder. Consequently, the power dissipation and hardware overheads of the Latch Adders are low. The Latch Adders may be controlled by Control Signals, which may be generated by Control Circuits. The application of the Latch Adders may be applied to the Final Stage Adder Circuit to further reduce spurious switching and thereby further reduce the power dissipation.

Abstract: A microelectronic apparatus and method for generating random binary words including at least one clocked pseudorandom binary number sequence generator normally operative to generate a cyclic output sequence of binary numbers, each number including a string of binary symbols, the cyclic output sequence including a basic sequence which is generated repeatedly, at least one bit stream generator generating a clocked bit stream including a stream of binary symbols of a first type occasionally interrupted by a binary symbol of a second type, wherein a first varying time interval between the occasional interruptions is intractably correlated to the output sequence of the number sequence generator, wherein each occurrence of an interruption of the stream of binary symbols of the first type by a binary symbol of the second type causes a pseudorandom modification of the cyclic output sequence of the number sequence generator and a sampling device operative to sample the cyclic output sequence of binary numbers thereby

Abstract: Apparatus for and methods of random number generation are disclosed, wherein a detector receives a group of n light pulses having single-photon intensity levels. Each of the n light pulses has a probability of less than one to produce a successful detection event at its time of arrival at the detector, and the detector is adapted to detect only one of the n pulses in the group. This single detection per group is thus a discrete random event that occurs only during one of n fixed time slots. The random event occurring during one of n timeslots is converted into a corresponding random integer from 1 to n. A series of such random numbers is generated by using a plurality of groups of n light pulses.

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract: In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented by a*(2^n) where a mantissa is a and an exponent is n, the mantissa is stored as a fixed point number in the upper U bits of N-bit field (N?(U+L)) and the exponent is stored as an integer in the lower L bits. For the multiplication of two real numbers represented in such a format, these two real numbers are multiplied as fixed point numbers so as to make only the upper significant bits of the multiplication result a mantissa, while these two real numbers are added as integers so as to make only the lower significant bits of the addition result an exponent. As a result, the multiplication result can be obtained in a floating point format.

Abstract: A method of modular exponentiation includes receiving as input a first number, a second number, and a modulus for calculating a residue of a product of the first number times the second number modulo the modulus; partitioning the first number into a selected number of pieces; calculating a first product of one of the pieces times the second number; adding a previous intermediate result to the first product to generate a first sum; shifting the first sum by a selected number of bit positions to generate a second product; and reducing a bit width of the second product to generate an intermediate result wherein the intermediate result has a bit width that is less than a bit width of the second product and has a residue that is identical to a residue of the second product modulo the modulus.

Abstract: A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.

Abstract: A method and apparatus for complex multiplication includes steps of: (a) receiving a complex multiplicand having a real value and an imaginary value (704); (b) generating a negation of the real value of the complex multiplicand (706); (c) generating a negation of the imaginary value of the complex multiplicand (708); (d) receiving a complex multiplier (710); and (e) selecting a phasor constant having a value wherein a complex product of the complex multiplicand times the complex multiplier times the phasor constant has a real value equal to one of the real value of the complex multiplicand, the imaginary value of the complex multiplicand, the negation of the real value of the complex multiplicand, and the negation of the imaginary value of the complex multiplicand (712).

Abstract: A microprocessor with multiple random bit generators is disclosed. The multiple random bit generators each generate a stream of random bits. One of the streams of random bits is selected to be used to accumulate into random bytes for provision to application programs. Which of the multiple random bit generator random bit streams is selected is determined by a selection value stored in a control register of the microprocessor. The selection value is programmable by an instruction executed by the microprocessor.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.