Abstract: A wireless power transmitting and charging system is disclosed. A method for operating a power transmitter of the wireless power transmitting and charging system comprises the steps of: maintaining a ping value table where ping signal conditions are mapped according to the height of a power receiver; recognizing the power receiver by varying a ping signal according to the ping signal conditions recorded in the ping value table; and controlling a charging mode according to a message received from the power receiver.

Abstract: A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.

Abstract: A notch filter is coupled to a first input node and a second input node, and is configured to present a capacitive load to a differential signal provided to the first and second input nodes, and to present a series-resonant inductive-capacitive load to a common-mode signal provided to the first and second input nodes. The notch filter includes a transformer and a capacitor bank. The transformer includes a first winding having a positive-polarity terminal coupled to the first input node and a second winding having a positive-polarity terminal coupled to the second input node. The capacitor bank includes a first capacitor coupled between a negative-polarity terminal of the first winding and a bias node, and a second capacitor coupled between a negative-polarity terminal of the second winding and the bias node. The first and second capacitors may be variable capacitors.

Abstract: A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.

Abstract: According to the present invention, an optical latch circuit includes a voltage detector configured to compare a first power generation voltage input from a first input terminal with a preset first threshold voltage and output a set signal from a determination output terminal when the first power generation voltage exceeds the first threshold voltage, a first photovoltaic element connected between the first input terminal and a grounding point in a forward direction and configured to output a first power generation voltage to the first input terminal according to photovoltaic power when light is radiated, and a feedback resistor inserted between the first input terminal and the determination output terminal.

Abstract: A radio frequency circuit includes: an amplifier circuit configured to amplify a first radio frequency signal using a first power supply voltage, and amplify a second radio frequency signal using a second power supply voltage. The first radio frequency signal is a signal in a first band for Long Term Evolution (LTE), the second radio frequency signal is a signal in a second band for 5th Generation New Radio (5G NR) or a wireless local area network (WLAN) signal, and in a state in which a first predetermined condition regarding the first radio frequency signal and the second radio frequency signal is satisfied, a value of the second power supply voltage is greater than a value of the first power supply voltage.

Abstract: An acoustic wave filter device includes a first longitudinally coupled acoustic wave resonator including an odd number of first IDT electrodes arranged along an acoustic wave propagation direction and a second longitudinally coupled acoustic wave resonator including an odd number of second IDT electrodes arranged in the acoustic wave propagation direction. Among the first IDT electrodes, the odd-numbered IDT electrodes are connected to a node and the even-numbered IDT electrodes are connected to a node. Among the second IDT electrodes, the odd-numbered IDT electrodes are connected to the node and the even-numbered IDT electrodes are connected to the node. The number of first IDT electrodes connected to the node and the number of second IDT electrodes connected to the node are the same.

Abstract: A non-transitory processor-readable medium stores instructions to be executed by a processor. The instructions cause the processor to receive a first trained machine learning model that generates a transcription based on a document. The instructions cause the processor to execute the first trained machine learning model and a second trained machine learning model to generate a refined transcription based on the transcription. The instructions cause the processor to execute a quality assurance program to generate a transcription score based on the document and the transcription. The instructions cause the processor to execute the quality assurance program to generate a refined transcription score based on the refined transcription and at least one of the document or the transcription. The at least one refined transcription score indicates an automation performance better than an automation performance for the at least one transcription score.

Abstract: During an ON period of a high breakdown voltage switch provided within an ON period of a semiconductor switching element, a detection circuit outputs to a predetermined node a voltage obtained by dividing an inter-terminal voltage by a plurality of resistor elements. A voltage comparison circuit outputs a detection signal indicating whether or not the inter-terminal voltage is greater than a predetermined determination voltage based on a comparison between the voltage of the predetermined node and a predetermined DC voltage. The high breakdown voltage switch has a breakdown voltage greater than a potential difference between a high potential and a low potential during an OFF period.

Abstract: A semiconductor device includes: first and second power transistors connected in parallel with each other and having different saturated currents; and a gate driver driving the first and second power transistors with individual gate voltages, respectively, the gate driver includes a drive circuit receiving an input signal and outputting a drive signal, a first amplifier amplifying the drive signal in accordance with first power voltage and supplying the amplified drive signal to a gate of the first power transistor, and a second amplifier amplifying the drive signal in accordance with second power voltage different from the first power voltage and supplying the amplified drive signal to a gate of the second power transistor.

Abstract: A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

Abstract: An apparatus is provided comprising a first t-switch, which includes an input port arranged to be connected to a first voltage source, a center-tap port, and an output port arranged to be connected to a load. The first t-switch is configured to connect the input port to the output port in an on mode and disconnect the input port from the output port in an off mode. The apparatus further comprises a bias voltage generation circuit configured to generate a bias voltage, the generated bias voltage coupled to the center-tap port of the first t-switch, the bias voltage determined based upon an output port voltage.

Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

Abstract: Systems, devices, and methods related to phase shifters are provided. An example apparatus includes a first node to receive an input signal, a second node, a first signal path coupled between the first node and the second node, and a second signal path coupled between the first node and the second node. The first signal path includes a positively coupled transformer. The second signal path includes a negatively coupled transformer. The second signal path is out-of-phase with the first signal path at the second node. The apparatus further includes a plurality of switches to select the first signal path or the second signal path. The apparatus may further include tuning capacitors to improve phase-shifting performance of the apparatus.

Abstract: The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

Abstract: A method and device for adjusting the switching speed of a MOSFET are disclosed. The MOSFET is connected to drive switch, the collector of the drive switch is connected to the grid of the MOSFET through the grid resistor, the emitter of the drive switch is grounded through the emitter resistor, and the collector of the drive switch is also connected to the source resistor through the collector resistor, the other end of the source resistor is connected to the source of the MOSFET; the drain of the MOSFET is connected to the current source. The method comprises: obtaining the adjustment target of the switching speed for the MOSFET, determining the first resistance value of the emitter resistor and/or the second resistance value of the collector resistor based on said adjustment target, controlling the operation of the MOSFET according to the adjusted resistance value.

Abstract: Methods, systems, and devices for controlling a variable capacitor. One aspect features a variable capacitance device that includes a capacitor, a first transistor, a second transistor, and control circuitry. The control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations including detecting a zero-crossing of an input current at a first time. Switching off the first transistor. Estimating a first delay period for switching the first transistor on when a voltage across the capacitor is zero. Switching on the first transistor after the first delay period from the first time. Detecting a zero-crossing of the input current at a second time. Switching off the second transistor. Estimating a second delay period for switching the second transistor on when a voltage across the capacitor is zero. Switching on the second transistor after the second delay period from the second time.

Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

Abstract: A method and apparatus for implementing a neural network model in a heterogeneous computing platform are disclosed. The method includes partitioning a neural network model into first sub-models based on a partition standard, obtaining second sub-models by merging at least a portion of the first sub-models based on characteristics of the first sub-models, and deploying the second sub-models.

Abstract: One embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising creating a global view of communication operations to be performed between the multiple compute nodes of the distributed compute system, the global view created using information specific to a machine learning model associated with the distributed compute system; using the global view to determine a communication cost of the communication operations; and automatically determining a number of network endpoints for use in transmitting the data between the multiple compute nodes of the distributed compute system.