Abstract: Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other, the source and destination buffer names are contained right in the transmitted packet.The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed.

Abstract: A data processing system in which macroinstructions are decoded to provide a sequence of microinstructions comprising one or more microroutines. If a fault condition occurs, the currently executing microinstruction of a sequence thereof is interrupted, while the fault is being handled. When the fault has been resolved, execution of the interrupted microinstruction resumes. If the fault cannot be resolved the sequence of microinstructions is permanently aborted. The process of interrupting the sequence and resuming operation at the interrupted microinstruction is essentially invisible to the microprogram.

Abstract: A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes.

Abstract: A priority circuit handles requests by three components of a data processing system for access to several resources of the system that can be accessed one at a time on each operating cycle of the system. A logic circuit receives requests by the requesters and grants access to one requester on a priority basis. The logic circuit has means for establishing a particular priority sequence, and the priority circuit includes means for stepping the logic circuit through a cycle of different priority sequences. In a repeating cycle of these steps, each requester is given the highest priority at least once. In a specific embodiment, the stepping means is a counter and a cycle is called a counting cycle. The stepping means is responsive to a control code to establish a particular stepping sequence.

Abstract: A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in a name table which contains information from which the processor determines the location and the format for the data. The name table entry specifies a base address of one of a set thereof which change value only when a call or a return instruction is executed. A name interpretation system fetches a name table entry, calculates the base address and a displacement using the name table entry and the current architectural base address and adds the base address to the displacement to form the address of the data represented by the name.

Abstract: An interface module and associated software connect a broad range of computer systems to a real time local area network. It connects to a host computer system that needs only to use parallel data input/output ports in order to communicate with the module. Hardware on the interface module accomplishes transmitting data to and receiving data from the local area network, all of these transfers of data being via a buffer memory. The interface module is capable of transmitting and receiving serial data at a rate of ten megabits per second, can store approximately 14 kilobytes of this data internally in the buffer memory, and can then transfer the data to or from a host computer system at a rate of 16 bits every 719 nanoseconds. A graphics processor is used to drive real-time graphics displays in the cockpit of a simulator and the module of this invention interfaces the graphics processor to a minicomputer.

Abstract: A single chip microcomputer responsive to internal and external instructions in normal and debug modes, respectively, comprises a program counter and first, second, third, and fourth port groups in both of the normal and the debug modes. The first through the fourth port groups are operable in the normal mode to process each internal instruction. Master and slave modes are defined in the debug mode to selectively change operations of the first through the fourth port groups by the use of port controllers to process each external instruction. The master mode is specified by using the first and the second groups as an instruction input port group for each external instruction and as a transfer bus for data related to each external instruction, respectively. In contrast, the third and the fourth port groups are used as an instruction input port group and a transfer bus, respectively. The master and the slave modes are indicated through a single terminal used in the normal mode.

Abstract: Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.

Abstract: The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.

Abstract: A method and apparatus for writing a vector of data into a random access memory at high speed wherein the random access memory (RAM) is partitioned into blocks of addressable storage sites and wherein storage sites within each block are individually accessible. A vector generator provides addressing and storage site enabling signals to the RAM. Boundary detectors monitor the addressing and storage site selection signals to determine whenever storage sites within a new block of storage sites are sought to be addressed. When a boundary transition is detected, a control signal is provided to the vector generator which slows the operation of the vector generator for a period of time sufficient to permit the RAM to accept a new address. For all other addresses, the vector generator is permitted to operate at a higher speed wherein access to the RAM is made by way of enabling specific storage sites within the block of storage sites being written into.

Abstract: A microprogrammed data processor in which the average processing speed is significantly enhanced by very rapidly processing system-initiated control operations using multiplexed programmable logic arrays. A wide input system encoding programmable logic array (270) responds to input signals which instruct system-initiated control operations, such as interrupts, power failure shut-down operations, system reset operations, ets., to produce internal exception condition opcodes. These opcodes are applied to inputs of a plurality of system decode programmable logic arrays (251-254) which, in response to the opcodes, generate sequences of microwords for executing the system-initiated control operations. The system decode programmable logic arrays (251-254) are activated sequentially and cyclically to generate the sequences of microwords used to carry out each of the control operations.

Abstract: A digital computer system having a memory system organized into objects for storing items of information and a processor for processing data in response to instructions. An object identifier code is associated with each object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in the name table associated with the procedure. The name table for a name contains information from which the processor may determine the location and the format for the data (e.g., an operand) represented by the name.

Abstract: Encachement apparatus comprising a plurality of frames which include registers for storing data, one of which frames is selected as a current frame, the encachement apparatus responding to a key for outputting data from the registers in the current frame. The current frame is selected from a succession of frames and during a call operation a new current frame is selected as the frame following the current frame and during a return operation a new current frame is selected as the frame preceding the current frame.

Abstract: Encachement apparatus for use in a processing unit which is responsive to data items which include first and second component values, while values change in response to first and second operations, respectively, of the processing unit. The encachement apparatus comprises first and second caches for storing and outputting first and second component values of such data items which values are combined to form the data items involved.

Abstract: A multi-function high speed barrel shifter comprising three functional levels. The first level performs 1/4 word shifts by a selectable amount. The second level performs 1/8 word shifts on the portion of the word to be shifted and, where desired, fills the remainder of its output with fill bits. The third level performs 1/32 of a data word shift. All shifting and filling are controlled by an input control signal which specifies the operation, direction and shift amount. The circuit is easily complimented in LSI Technology and is easily cascaded to double the size of the data word handled thereby.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having a combined on - chip read/write memory for macrocode and microcode storage. A macrocode word is fetched from the memory and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the same memory based on this macrocode word. Both macrocode and microcode may be loaded into the combined memory from external to the chip, so the functions of the microcomputer may be changed for different tasks. The content of both microcode and macrocode, as well as the ratio of macrocode to microcode, can be varied by programming without any change in the circuitry of the chip.

Abstract: A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.

Abstract: An electronic translator comprises a specifying device for specifying letters to be input. An input device cooperates with the specifying device to input the specified letters into the electronic translator. The translator also includes a memory for memorizing a plurality of words containing the input letters, an access circuit for addressing the memory to retrieve such words and a display responsive to the access circuit for displaying the retrieved words and translated equivalent words. The specifying device is operated with only a few keys to enable input of any letter of the alphabet.

Abstract: Several I/O channel processes time share a data pipeline processor. For each stage of the pipeline, there is a control memory and means for shifting an address from memory to memory as a process in the pipeline proceeds from stage to stage. The number of processes is greater than the number of pipeline stages, and storage is provided for the data and for the addresses while a process is out of the pipeline, waiting to be re-entered for a next pass. A storage array for holding the addresses is arranged to hold addresses for four activity levels for each process. While an address is held in the array it can be modified for the next pass through the pipeline or the process can be switched from a lower priority level activity to a higher level activity.

Abstract: A method and apparatus for writing a vector of data into a random access memory at high speed wherein the random access memory (RAM) is partitioned into blocks of addressable storage sites and wherein storage sites within each block are individually accessible. A vector generator provides addressing and storage site enabling signals to the RAM. Boundary detectors monitor the addressing and storage site selection signals to determine whenever storage sites within a new block of storage sites are sought to be addressed. When a boundary transition is detected, a control signal is provided to the vector generator which slows the operation of the vector generator for a period of time sufficient to permit the RAM to accept a new address. For all other addresses, the vector generator is permitted to operate at a higher speed wherein access to the RAM is made by way of enabling specific storage sites within the block of storage sites being written into.