Abstract: A peripheral-controller (called a Data Link Processor) optimizes the rate of data transfers between a host computer and magnetic tape peripherals by use of a block counter sensing system for monitoring the occupation-status of word-blocks in a buffer memory. The peripheral-controller provides Automatic Read/Write Logic for buffer-peripheral tape transfers and a burst mode routine for rapid host-buffer transfers of data words. The sensing system provides means to inform a microcode sequencer when certain action routines should be executed in order to maintain steady error-free data transfer operations which minimize the need for retries of data transfer cycles previously initiated.

Abstract: A computer architecture wherein data inputs causes the dynamic creation of appropriate activities employing stored functions as necessary to accomplish the desired end result for the data. The architecture employs a large scale multi-processing environment for parallel computation. A fast forward propagating queue structure and improved interfacing crossbar are employed.

Abstract: An interface facilitating data transmission between a control processor, connected to an asynchronous two-way bus, and a plurality of terminals, connected to a common synchronous two-way bus, comprises a microprocessor responsive to periodically recurring access requests from the several terminals. The access requests are short pulses with a recurrence period greatly exceeding their duration, this period being nominally equal for all terminals and sufficient to accommodate one data transfer to or from each terminal with time remaining for execution of part of a main program performed by the control processor. Coinciding access requests from different terminals are handled according to a predetermined order of priority. The exchange of data takes place by way of a data memory and a buffer memory linked by an internal two-way bus. Data transfer between the control processor and a terminal takes place in three stages, i.e.

Abstract: A data communication system comprises a plurality of terminal units having different addresses individually and a main control assembly connected to the terminal units by transmission lines for controlling the terminal units. The terminal units include a first group of terminal units and second group of terminal units. The main control assembly controls the first group of terminal units according to a series of instructions for controlling the units in a predetermined sequence. When executing one instruction, the main control assembly performs data communication with only the one specific terminal unit relevant to the instruction. Concomitantly with the communication with the specific terminal unit, the main control assembly scans and communicates with the second group of terminal units only during periods that specified conditions exist. In addition, means are provided for communicating malfunction information between the main control assembly and the terminal units.

Abstract: A minicomputer system is disclosed having a bus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling an alternate route for issuing instructions from one processor to another. The logic detects information that is not to be transferred to the I/O devices and accordingly reroutes it back to the central processor and/or subprocessors.

Abstract: In a computer system, an improved memory circuit is provided for accomodating video display circuits with CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accomodate any CRT screen intended to be used, and it further includes a serial shift register having a plurality of taps at locations corresponding to different preselected columns of cells in the chip. In the system, provision is included for selecting taps to unload only the portion of the shift register containing the bits of interest, whereby unused portions of the chip may be effectively excluded and the time for transferring data of interest to the CRT screen is reduced.

Abstract: A storage-management program, executable in one host or simultaneously in a plurality of hosts, manages concurrently executing migration, recall, and recycle (such as defragmentation) tasks. Accesses to data storage volumes (tape, disks, etc.) are managed in accordance with predetermined contention resolution procedures and priorities. Certain tasks are non-interruptible.

Abstract: A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step.

Abstract: A digital processor system including several function modules where each modules includes circuitry to perform at least one computational task and circuitry to transfer information containing that module's respective computational task capability to a logical arbiter upon initialization. Each module further includes circuitry to interface to the logical arbiter upon initialization to determine that module's address. Further disclosed is an information bus that connects all function modules together with the logical arbiter. The presence of the logical arbiter provides for a self-configuration capability upon initialization.

Abstract: A technique for providing a partial memory of one half of the possible storage bits comprised of any two quadrants is implemented by decoupling the one of four decoder used for normal operation and providing a programmable decoder which is capable of being programmed to select one of any two quadrants. If only one quadrant is to form the partial memory, the programmable decoder can be programmed to select only one latch. In another embodiment, a decoder is provided which can also be programmed to select one of any three quadrants.

Abstract: A data processing system having a data bus with a two-byte capacity provides for the DMA transfer of both one-byte data and two-byte data between a memory and an input/output adapter. An address counter and a byte counter receive a start address and a byte number indicating the number of bytes to be transferred, respectively, through the system bus from the processor. The least significant bits in the start address and the byte number are used to control whether the data transfer on the bus will be a one-byte transfer or a two-byte transfer for the first transfer operation and the last transfer operation.

Abstract: The apparatus comprises an electronic teleprinter constituted by a first set of basic peripheral units such as the printer, keyboard etc. as well as a punch/reader, arranged to converse directly with the line and controlled by a first central unit, and a second set of peripheral units such as a disc unit, one line display and VDU controlled by a second CPU and able to execute more sophisticated operations such as the automatic filing of messages, their display etc. The two CPUs each autonomously control their own peripheral units with simultaneous processing, and periodically communicate with each other for the exchange of data and commands by way of an interface in an auxiliary unit. The CPU of the basic machine is thus free to handle the basic input/output procedures without having to service the auxiliary peripherals.

Abstract: A relatively low cost, high speed search processor for efficiently scanning, inserting, and clearing certain data in an ordered linked list of data regarding a plurality of video scan line segments, which segments define mathematical elements (e.g. polygons) and corresponding portions of a three dimensional image. Data items containing information regarding the starting coordinates of the segments of a scan line are encoded and stored in the linked list according to the magnitudes thereof. The present search processor is adapted to read a new data entry to the linked list which is representative of the magnitude of a scan line segment starting coordinate and rapidly search the existing data items of the linked list to determine a particular location in the list at which to insert the new data entry, depending upon the magnitude of the scan line segment starting coordinate thereof relative to the magnitudes of the respective scan line segment starting coordinates of other items in the list.

Abstract: An electronic translator is featured in which a particular sentence, phrase or idiom is accessed from a memory utilizing at least two key words. The key words are contained with the particular sentence, phrase or idiom. The translator is adapted to identify that a sentence, phrase or idiom stored in the translator contains one of the key words each time one of the key words is inputted.

Abstract: Herein disclosed is a digital semiconductor integrated circuit which is equipped with: a digital signal input circuit; an analog signal input circuit made receptive of an analog signal for feeding out a digital signal corresponding to said analog signal; and a common external terminal connected commonly with the input terminals of said digital signal input circuit and said analog signal input circuit. By the operation with the use of a suitable switch circuit, the aforementioned common external terminal can be used as either an analog signal input terminal or a digital signal input terminal. As a result, the number of the external output terminals required for the aforementioned semiconductor integrated circuit can be reduced.

Abstract: A method and apparatus for identifying the failing equipment in a computer system when a failure condition is experienced by a computer operator while accessing a computer input/output channel. The apparatus has a memory system which records pre- and post-failure events, which recordings are used for analyzing signal activity on the input/output channel. The signals retained in memory may be output to a hard copy device in an easily understood format to provide a picture or input/output bus activity for the time surrounding the failure event. The operator may utilize the hard copy output to rapidly diagnose the cause of computer failure.

Abstract: A processor control system for controlling items of hardware includes pairs of processors associated with the hardware items. One processor of each pair operates the process or processes for controlling the associated hardware, while the other processor of each pair operates other processes. In the event of a fault in one processor the processes on that processor are transferred to spare processors and the hardware control process is transferred to the other processor of the pair. This arrangement makes more effective use of standby processing capacity.

Abstract: Apparatus for producing programmable timing signals, having a microprocessor element with means for carrying out DMA operations when said microprocessor element is in a DMA mode, memory interconnected with said microprocessor element and containing a stored program and a plurality of data words stored at predetermined addresses for selection by said microprocessor when in said DMA mode, comprising controller means for transforming received data words into timing signals, connecting means for interconnecting said microprocessor element, said controller and said memory, said controller having means for setting said microprocessor in said DMA mode upon receipt of a predetermined signal generated by said program, means for receiving data words directly from said memory under control of said microprocessor when said microprocessor is in said DMA mode, and means for generating a two state timing signal corresponding to the data content of one or more such received data words.

Abstract: A multiprocessor system includes a plurality of processors which are respectively connected to a memory device and each of which produces a first control signal when executing a test-and-set instruction and a second control signal after executing a sequence of queuing steps. The multiprocessor system further has flip-flop circuits each of which is set in response to the first control signal from the corresponding one of the processors and which are commonly reset in response to a secnd control signal from any one of the processors. The processors are prevented from executing the test-and-set instruction while the corresponding one of the flip-flop circuits is set.

Abstract: The processor of the present invention can execute any of a plurality of dialects of "S-Language" instructions. S-Languages are of a higher order than typical machine languages but of a lower order than the user's own high order language. They can be tailored for compatibility with user high order languages. Each instruction of a particular S-Language is interpreted by a sequence of microinstructions. In the processor of the present invention, dispatching to the microinstruction sequencer is controlled jointly by the instruction bit pattern and the current contents of a dialect register. Each procedure to be executed carries with it information from which the appropriate contents of the dialect register may be determined. Thus, the processor of the present invention can always operate as an effective optimum processor for executing the procedure regardless of the source language chosen for writing that procedure.