Abstract: Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

Abstract: An input processor such as table calculator comprises input means for putting numerical data in said processor; memory means for storing first n-digit numerical data put in by said input means; reading means for reading out said stored first n-digit data from said memory means and processing means for arranging said first n-digit numerical data read out by said reading means and second m-digit numerical data newly put in by said input means in neighboring relation thereby forming a new n+m-digit numerical data therefrom.

Abstract: Data is transmitted asynchronously between a master and a slave microprocessor unit by first converting the number representing the word or part thereof to be transmitted into a time interval, transmitting a pulse having a width corresponding to the time interval and, at the receiver, reconverting the pulse width (time interval) to a number. Conversion and reconversion can be accomplished by, respectively, down counting a counter with a fixed frequency from the number constituting the word to be transmitted and up-counting a counter during the received pulse width at the same frequency.

Abstract: Apparatus for rapidly transferring data between a central processing unit (CPU) of microcomputer apparatus and floppy disc drives, includes a floppy disc controller for interfacing the floppy disc drives with the CPU and generating an interrupt request status signal indicating whether a command has been executed and a data request status signal indicating whether data is to transferred between the floppy disc controller and the CPU, the CPU generating command signals in response to these status signals; a data bus connecting the CPU to data access lines of the floppy disc controller; a bidirectional buffer interposed between the data bus and the data access lines for gating the data between the floppy disc controller and the CPU through the data bus and for gating the interrupt request status signal and data request status signal through the data bus to the CPU in response to gating signals; first and second gate circuits for gating the status signals to the buffer in response to the gating signals; a NOR gat

Abstract: In a data processing system there are provided a main memory device for storing information, a plurality of buffer memory devices including a plurality of blocks for storing a copy of information stored in the main memory device, an arithmetic operation controller including at least one block corresponding to at least one of the blocks of the buffer memory devices for executing instructions including a branch instruction, a branch direction control memory device for storing branch direction information obtained by executing the branch instruction and a preceding controller. The preceding controller comprises a read out means for reading out from the buffer memory devices branch direction information together with a prefetched instruction predicting means for predicting whether a branching will be successful or not.

Abstract: A method and control apparatus for operating an interactive text processing system wherein the system emulates a terminal for a data processing system which is capable of accessing information from the data processing system data base, copying the information into the text processing system memory, and automatically converting the information from the data processing system format into the text processing system format. Similarly, the text processing system is capable of converting information from its own data base from a text processing system format to a data processing system format and transmitting the information to the data processing system.

Abstract: An electronic security system for a device requiring an external power source is disclosed. The security system includes a microcomputer which executes a power-on routine stored in memory whenever the microcomputer is initially coupled to a power source. The user must enter a primary security code which is compared to a predetermined code, and if the codes match, the microcomputer signals a relay to provide power to the device, thereby enabling it. Once enabled, the user need not reenter the security code as long as the external source of power to the device remains uninterrupted. A secondary security code may be entered if the primary code has been forgotten or misplaced. Upon entry of the secondary code, the microcomputer displays an encrypted version of the primary security code. If an incorrect code is entered by the user, the microprocessor executes an alarm routine which may include visual and audible warnings.

Abstract: A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.

Abstract: A digital processing system including a nonvolatile memory for the storage of instructions and data where the memory contains a plurality of field effect transistors which selectively conduct current according to the electrical state of their gates and the doping of their channel regions. Also included is a central processing unit for performing operations on data connected to an information transfer bus which is in turn connected to the nonvolatile memory. The information bus is additionally connected to an external interface circuit that provides interface to external peripherals. The memory is programmed by the doping of the channel regions instead of the fabrication or nonfabrication of the gates. Therefore, data that is stored in the memory is invisible to one examining the memory itself. This allows protection to software stored in the permanently programmed memory.

Abstract: A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.

Abstract: Arbitration as provided in two separate levels, first between two signals that may contend for access to a system resource, such as a memory, and second between the winner of the first arbitration and another source, such as a refresh signal timer, that must have access to the system resource periodically and independently of requests for access from the other signals. The winning signal of the first arbitration is not continuous but is divided into intervals, and the refresh timer gains control of the second arbitration at the end of each interval of control by the winning signal from the first arbitration.

Abstract: An electronic translator has the capability of controlling an access circuit so as to retrieve words or sentences stored in a memory in a forward direction or a backward direction, in order that an access time to the words or sentences is reduced.

Abstract: A postage calculator system and method comprising means for introducing postal information to the system; a means for obtaining weight information of the article to be mailed; a memory means for storing information indicative of special feed categories; and means for generating a postage value for the article from the postal information, the weight information and the special fee information. The system selects postal information indicative of the carrier type, class and destination of an article to be mailed, obtains weight information for the article, selects special fee information indicative of at least one of the following special fee categories for use with the article: registered mail, special delivery, return receipt, certified mail, insurance and C.O.D. The system then generates a postage value, adjusted in accordance with the special fees, if any, determined, for the article.

Abstract: A memory refresh control scheme is provided wherein the refresh timing and address signals are independent of memory configuration or the configuration of an interface unit. Since the system relates to a distributed memory arrangement, the refresh control signal and the refresh address signals are simultaneously sent to the corresponding address portions of each of the concerned memory sections and to the interface units. The logic involved in generating the refresh signal includes a first counter, driven by the system clock, which periodically generates the refresh request control signal. A second counter generates a digital address for the portion of the memory units to be refreshed. The second counter is incremented by each successive output control signal from the first counter.

Abstract: Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s).

Abstract: A process for assuring that the individual computational elements of a fault-tolerant computer system have the same view of the external world when applied in applications where input data representations of the same quantity may have slight variations without being incorrect. The process transmits data between each of the computational elements through circuitry utilizing transmitters and receivers, and provides a check as to the accuracy of each such transmission, resulting in each computational element either having the same plurality of data as each other computational element, or a representation that a transmission was faulty.

Abstract: A multi-microprocessor apparatus utilizing a plurality of central processing units arranged in a parallel configuration. Each central processing unit which has its own local memory unit, communicates with a common memory unit on a time shared basis that is synchronized between each central processing unit and the common memory unit.

Abstract: A digital processing device implemented on a single semiconductor substrate includes an nonvolatile memory for the storage of data and instructions that define operations on the data. The memory is connected to an inhibit logic interface which is in turn connected to an information bus. The information bus is connected to a central processor that performs the operations on data. An external interface is also connected to the information bus to provide information on the information bus to external devices. At least one security bit is provided for designating security status of information stored in the memory. Address logic is connected to the information bus to determine when information is being accessed from the memory. Security control circuitry is also provided and is connected to the central processing unit, the address logic, to determine when an instruction is being fetched by the central processing unit and if the instruction is being fetched from the memory.

Abstract: A character generator for a raster printer which prints in the page mode. Input format data is generated in response to the input print data which defines for each pattern the position of the pattern on the page, the size of the pattern and the location of the pattern in the raster pattern storage. The format data is accessed for all patterns beginning within a predetermined plurality of scan lines and raster data is accessed in response to the format data to store in an output buffer the raster pattern data in the sequence, size and position defined by the format data. The raster pattern data can then be accessed to control a printer to print on a print medium a pattern defined by the input print data.

Abstract: A sequencing apparatus and method employing two or more control stores for use within a data processing system. Where two-way branching exists, first and second control stores each provide control words for the common control of units within a data processing system. Whenever a branch is specified, a corresponding branch address is provided in the first control store for addressing the second control store. A nonbranch address is provided for addressing the first control store. The nonbranch address and the branch address each are employed to access concurrently control words from the first and second control stores. Upon the determination of the state of the branch condition, the appropriate one of the previously accessed control words is selected without delay and without need for an additional cycle to access the control stores.