Abstract: A computer system may create a language model corpus including multilingual alignment for training a combined language model and train (or pre-train) the combined language model. The computer system may create an adverse medication reaction corpus to include adverse medication reaction utterances and label an N-gram of an utterance in the adverse medication reaction utterances as a response to query, for multiple N-grams. The computer system may generate a code-mixed utterance model to perform code-mixed utterances in a turn by turn dialogue, by at least adding additional output layer including at least a start vector, language vector, and a query vector including at least the labeled N-gram, which are additional to the combined language model's predicted next words.

Abstract: According to one embodiment, a voice activity detection apparatus comprises a processing circuit. The processing circuit calculates an acoustic feature based on an acoustic signal; calculates a non-acoustic feature based on a non-acoustic signal; calculates a correlation coefficient based on the acoustic feature and the non-acoustic feature; and detects a voice section and/or a non-voice section based on a comparison of the correlation coefficient with a threshold, the voice section being a time section in which voice is presence, the non-voice section being a time section in which voice is absence.

Abstract: Disclosed is an electronic device recognizing an utterance voice in units of individual characters. The electronic device includes: a voice receiver; and a processor configured to: obtain a recognition character converted from a character section of a user voice received through the voice receiver, and recognize a candidate character having high acoustic feature related similarity with the character section among a plurality of acquired candidate characters as an utterance character of the character section based on a confusion possibility with the acquired recognition character.

Abstract: A method of detecting live speech comprises: receiving a signal containing speech; obtaining a first component of the received signal in a first frequency band, wherein the first frequency band includes audio frequencies; and obtaining a second component of the received signal in a second frequency band higher than the first frequency band. Then, modulation of the first component of the received signal is detected; modulation of the second component of the received signal is detected; and the modulation of the first component of the received signal and the modulation of the second component of the received signal are compared. It may then be determined that the speech may not be live speech, if the modulation of the first component of the received signal differs from the modulation of the second component of the received signal.

Abstract: A non-transitory computer-readable recording medium having stored therein an update program that causes a computer to execute a procedure, the procedure includes calculating a selection rate of each of a plurality of quantization points included in a quantization table, based on quantization data obtained by quantizing features of a plurality of utterance data, and updating the quantization table by updating the plurality of quantization points based on the selection rate.

Abstract: A method and an apparatus for audio signal processing evaluation are provided. The audio signal processing is performed on a synthesized audio signal to generate a processed audio signal. The synthesized audio signal is generated by adding a secondary signal into a master signal. The master signal is merely a speech signal. The signal processing is related to removing the secondary signal from the synthesized audio signal. The sound characteristics of the processed audio signal and the master signal are obtained, respectively. The sound characteristics include text content, and the text content is generated by performing speech-to-text on the processed audio signal and the master signal. The audio signal processing is evaluated according to the compared result between the sound characteristics of the processed audio signal and the master signal. The compared result includes the correctness of the text content of the processed audio signal relative to the master signal.

Abstract: A method for decoding an encoded audio bitstream is disclosed. The method includes receiving the encoded audio bitstream and decoding the audio data to generate a decoded lowband audio signal. The method further includes extracting high frequency reconstruction metadata and filtering the decoded lowband audio signal with an analysis filterbank to generate a filtered lowband audio signal. The method also includes extracting a flag indicating whether either spectral translation or harmonic transposition is to be performed on the audio data and regenerating a highband portion of the audio signal using the filtered lowband audio signal and the high frequency reconstruction metadata in accordance with the flag. The high frequency regeneration is performed as a post-processing operation with a delay of 3010 samples per audio channel.

Abstract: With correct emotion classes selected as correct values of an emotion of an utterer of a first utterance from among a plurality of emotion classes C1, . . . , CK by listeners who have listened to the first utterance, as an input, the numbers of times ni that emotion classes Ci have been selected as the correct emotion classes are obtained, and rates of the numbers of times nk to a sum total of the numbers of times n1, . . . , nK or smoothed values of the rates are obtained as correct emotion soft labels tk(s) corresponding to the first utterance.

Abstract: A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elements and reconfigurable devices with course grained logic elements or a reconfigurable processor comprising both reconfigurable devices with fine grained elements and non-reconfigurable devices with course grained elements.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a switch for switching and connecting the multiple disk controllers containing cache memories, with a disk array containing the shared volumes capable of being commonly accessed from the multiple disk controllers. The switch performs exclusive access control of the multiple disk controllers' writing on the shared volumes, and performs control to match data other than modified data among the cache memories.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.

Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.

Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (xi AND xj), where xi=x1, x2, . . . xN?1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.

Abstract: Systems, methods, apparatus and software can utilize an extent guard to prevent modification (including relocation) of data in the storage resource while a third-party copy operation directed at the storage resource is occurring. A data transport mechanism such as a data restore application provides an extent list to the extent guard, which monitors read and/or write activity to storage resources described by the extent list. The data transport mechanism requests a data mover to perform a third-party copy operation whereby data is moved from a data source to the storage resource. If a modification attempt is made on the portion of the storage resource described by the extent list, the extent guard stalls the modification attempt until the third-party copy operation is aborted.

Abstract: A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.

Abstract: Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for uniquely identifying the oldest version, and (b) at least a most recently updated version of the set of data in a second, distinct memory area, the second memory area including at least one second tag for uniquely identifying the most recently updated version. The invention also relates to a computer arrangement including a processor and such a computer-readable medium, as well as to a method of updating sets of data having such tagged-data structures.

Abstract: An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or more specifiers. Each specifier relates to a different portion of the page, and maps from that portion of the page to a corresponding range of packet addresses. Accordingly, the unit allows for address translation to be performed with a sub-page granularity.

Abstract: The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.