Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

Abstract: The data processing system comprises at least one first storage system, and at least one second storage system connected to the first storage system. The second storage system receives change information identifying pre-change and post-change copy destination storage areas in a change process for changing a copy destination storage area of a target copy pair to another storage area of the second storage system; transmits the change information to the first storage system that has a copy source storage area in the target copy pair; and transmits copy information for the purpose of copying data between the pre-change and post-change copy destination storage areas. The first storage system refers to pair information identifying the copy pair, and transmits a copy of the data stored in a copy source storage area to the second storage system that has a copy destination storage area. The first storage system updates the pair information according to the change information received from the second storage system.

Abstract: A storage device can flexibly apply a dynamic load distribution and a performance expansion to an unexpected peak performance demand changing in a time sequence such as a web server and a contents delivery at the minimum cost. In the storage device, a load condition of a logical volume is measured by a performance measuring mechanism based on a data and command processing amounts transferred by a data transfer mechanism, and contents of the logical volume set in the physical volume are copied to a logical volume set in the auxiliary logical volume by a copy mechanism based on a measurement result of the performance measuring mechanism, and the logical volume set in the auxiliary physical volume copied by the copy mechanism and the logical volume set in the physical volume serving as a copy source are provided as one virtual logical volume in a host, thereby distributing a load from the host.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card.

Abstract: Methods and apparatus for maintaining an average erase count in a system memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for determining an average number of times each block of a number of blocks within a non-volatile memory of a memory system has been erased includes obtaining an erase count for each block that indicates a number of times each block has been erased. Once all the erase counts have been obtained, the erase counts are summed, and an average erase count that indicates the average number of times each block of the number of blocks has been erased is created by substantially dividing the sum by the number of blocks.

Abstract: A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover, the controller operable to detect an application write request to the block and to stall the application write request while a data move operation initiated by the data mover is terminated.

Abstract: A system, method, and computer program product are disclosed for prohibiting unauthorized access to a protected region of memory. A protected region of memory and a trusted region of memory are both specified. A call to access a location within the protected region of memory is received. An origination location of the call is then determined. In response to a determination that the origination location is within the trusted region, the call is permitted to access the protected region of memory. In response to a determination that the origination location is outside of the trusted region, the call is prohibited from accessing the protected region of memory.

Abstract: A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and the hit cache line is scanned for candidate virtual addresses in order to reinforce the prefetch chain.

Abstract: A first array of disk drives overlaps with a second array of disk drives in a Redundant Array of Inexpensive Drives (RAID) system, in which the first and second arrays share at least one disk drive. A first stripe of data from a first client is stored in the first array, and a second stripe of data from a second client is stored in the second array. The shared disk drives are less than the number of drives needed to reconstruct a full stripe. Thus, in the event of a drive failure in the first array, the first client can reconstruct the first data stripe, but is never able to reconstruct the second stripe. Likewise, in the event of a drive failure in the second array, the second client can reconstruct the second data stripe, but is never able to reconstruct the first stripe.

Abstract: When there is a change in a group of volumes managed by a host computer, data duplication processing is immediately carried out against the changed volume. The host computer includes a volume-managing portion, a data duplication-controlling portion which executes the data duplication of data stored in a volume in a main data center, and a data duplication storing portion which stores data necessary for the data duplication. The data duplication-controlling portion compares data held by the volume-managing portion with the data in the data duplication storing portion, and updates the data in the data duplication storing portion based on the data held by the volume-managing portion.

Abstract: A memory system system includes a single in-line memory module (SIMM) which contains a memory device and a signal transmission line connected between the memory device and a connection terminal, and a dual in-line memory module (DIMM) which contains two memory devices and a signal transmission line connected between the two memory devices and a connection terminal. A length of the signal transmission line of the SIMM is longer than a length of the signal transmission line of the DIMM. The load of the memory device of the SIMM is less than the load of memory devices of the DIMM, and the longer length of the signal transmission line of the SIMM increases a signal delay time of the SIMM to compensate for the different loads of the SIMM and DIMM memory devices. The longer length of the signal transmission line of the SIMM may further compensate for a signal transmission line connected between the first and second sockets which receive the SIMM and DIMM, respectively.

Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Abstract: Methods and apparatus for efficiently enabling pages within a block to be accessed are disclosed. According to one aspect of the present invention, a method for writing data into a first block in a non-volatile memory which includes pages that are grouped into groups which each include two or more pages involves determining when a first group is available to receive the data. When it is determined that the first group is available to receive the data, the data is written into a first page included in the first group. The method also includes determining when a second group is available to receive the data if it is determined that the first group is not available to receive the data, and writing the data into a second page included in the second group when it is determined that the second group is available to receive the data.

Abstract: A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.

Abstract: A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.

Abstract: An embodiment of the invention provides a method for creating a snapshot of a data store. A command to create a snapshot of an original data store, stored to a parent virtual logical unit (VLU), is received. A deferred propagation data structure (DPDS) is associated with the parent VLU. The DPDS is capable of containing data propagation records and separators, each data propagation record contains a previous version of one or more data blocks of the parent VLU, each separator contains a pointer to a particular child VLU storing a snapshot of the original data store and separating the data propagation records pertaining to the particular child VLU. A child VLU to store the copy of the original data store is created. A new separator containing a pointer to the child VLU is created in the DPDS. A search pointer pointing to the DPDS is implemented in the child VLU.

Abstract: Methods for storing replacement data in a multi-way associative cache are disclosed. One method comprises logically dividing the cache's cache sets into segments of at least one cache way; searching a cache set in accordance with a segment search sequence for a segment currently comprising a way which has not yet been accessed during a current cycle of the segment search sequence; searching the current segment in accordance with a way search sequence for a way which has not yet been accessed during a current way search cycle; and storing the replacement data in a first way which has not yet been accessed during a current cycle of the way search sequence. A cache controller that performs such methods is also disclosed.

Abstract: A method consistent with the present invention avoids data loss in a data object replication process. The method includes: creating an electronic data element comprising a first field having an identifier and a second field having a state of the identifier; setting the second field of the data element to a state indicating that the electronic data element may be accessed and assigned; assigning the identifier to one or more data objects; setting a shared lock on the electronic data element; storing the one or more data objects; and upon a commit of the storing of the one or more data objects, removing the shared lock and setting the state of the identifier to indicate that the one or more data objects may be replicated.

Abstract: A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.