Abstract: A bipolar transistor which is inherently bistable, is disclosed. This bipolar transistor has a structure such that the corresponding band diagram includes a first potential barrier within the collector, at or adjacent the base-collector interface. In addition, the band diagram also includes at least a second potential barrier within the collector.

Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: A thin film transistor includes a glass substrate on a surface of which a hydrogenated amorphous silicon (a-Si:H) film is formed. On the a-Si:H film, a source electrode and a drain electrode are respectively formed with a suitable interval between them. A gate electrode is formed positioned between the source electrode and the drain electrode. Insulation film is interposed between the gate electrode and the a-Si:H film. In a direct photo-CVD method using a low pressure mercury lamp, bandtail characteristics energy of the a-Si:H film is made less than 40 meV by controlling a decomposition region of a reaction gas, that is, the distance between the glass substrate and a gas supply port, whereby a thin film transistor having a good response is obtainable.

Abstract: A semiconductor device fabricated on an n-type substrate has a plurality of signal input terminals each associated with a protection circuit for preventing an internal integrated circuit from being damaged by an undesirable surge voltage. The protection circuit is formed in a p-type well and comprises an n-type impurity region supplied with the surge voltage, an inner well contact area located inside of the n-type impurity region and an outer well contact area located outside of the n-type impurity region, so that a large amount of current flows from both side surfaces of the n-type impurity region into the inner and outer well contact areas, thereby decreasing the voltage level in the p-type well for preventing the p-n junction between the well and the substrate from destruction.

Abstract: A schottky diode consists of a substrate from gallium/arsenide (5) on which epitaxially a monocrystalline gallium/arsenide layer (6) doped with silicium is applied. For creating the Schottky contact, a monocrystalline erbium/arsenide layer or ytterbium/arsenide layer (7) is epitaxially applied on this layer. Following as a covering layer is a highly doped gallium/arsenide layer (8).

Abstract: A semiconductor device exposed to irradiation (21, 22) of charged particles in a fabrication process thereof includes: at least a first conductive region (3, 1) and a second conductive region (4a, 4b) formed at different positions, electrically insulated from each other; a third coductive region (8 , 9) provided at least over the first conductive region (3, 1) and the second conductive region (4a, 4b); a first insulator layer region (5, 7) sandwiched between the first conductive region (3, 1) and the third conductive region (8, 9) to insulate the first and third conductive regions from each other; and a second insulator layer region (6a, 6b) sandwiched between the second conductive region (4a, 4b) and the third conductive region (8, 9) to insulate the second and third conductive regions from each other, and the second conductive region (4a, 4b) has a portion shaped to cause dielectric breakdown to be more liable to occur in the second insulator layer region (6a, 6b) than in the first insulator layer region (5

Abstract: A semiconductor device includes a shield layer selectively formed to cover, via an insulating film, source and drain regions, a control gate electrode, first and second conductive layers and parts of first, second and third polycrystalline silicon layers. The shield layer has a portion which is in contact with the semiconductor substrate and the third polycrystalline silicon layer to surround the source and drain regions, floating and control gate electrodes, the first and second conductive layers and the parts of the first and second polycrystalline silicon layers.

Abstract: A lateral conductivity modulated MOSFET comprises a semiconductor wafer, a first-conductivity type base layer selectively formed in a surface region of the semiconductor wafer, a second-conductivity type source layer selectively formed in a surface region of the first-conductivity type base layer, a second-conductivity type base layer selectively formed in the semiconductor wafer, a first-conductivity type drain layer formed in a surface region of the second-conductivity type base layer, a gate insulation film formed on that surface portion of the first-conductivity type base layer which is sandwiched between the source layer and the second-conductivity type base layer, a gate electrode formed on the gate insulation film, a source electrode in contact with both the source layer and the first-conductivity type base layer, and a drain electrode in contact with the drain layer.

Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. N-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.

Abstract: A LOCOS isolation film is formed on a major surface of a semiconductor substrate. Thereafter, a new surface of the semiconductor substrate is exposed by wet etching. A resist pattern is formed on the exposed new surface. A part of the LOCOS isolation film is removed using this resist pattern, to expose the surface of the semiconductor substrate. This unsymmetrical LOCOS isolation film increases the effective area of the surface of the semiconductor substrate and preserves predetermined dielectric resistance.

Abstract: A semiconductor heterostructure useful as a photodetector in the far infrared. The barrier layers of the heterostructure are doped os that charge carriers migrate from the energy bands of the barrier layers towards the energy bands of the quantum wells, but remain weakly bound to the doping impurities in the barrier layers. Because of weak residual bonding, the energy necessary to raise these electrons fully into the quantum wells' energy band is significantly reduced, extending the lower frequency range at which such devices are useful as photodetectors. Selection of several of the heterostructure's dimensions determine the impurities' resonant absorption frequency, and application of an electric or magnetic field shifts the well's resonant absorption frequency, in effect frequency fine tuning the heterostructure.

Abstract: The UPROM memory cell comprises self-aligned lines of source and lines of drain obtained in a semiconductor substrate. It also comprises a strip of floating gate, a strip of dielectric and a strip of barrier polysilicon, each of these strips being provided with a respective pair of small lateral fins. The UPROM cell lastly comprises a control gate superimposed over and self-aligned with the floating gate.

Abstract: Interleaved arrays of photoelectronic devices are fabricated utilizing one-step epitaxial growth of all active layers and simple planar processing. Exemplary arrays include interleaved LED transmitters and PIN photodiode receivers that operate at the same wavelength on light that enters the PINs and exits the LEDs along opposite but parallel paths and interleaved arrays of LED transmitters that emit light at two different wavelengths.

Abstract: An insulated gate field effect device is disclosed having a channel region which includes both a horizontal and a vertical portion. The device is fabricated on a semiconductor substrate having a recess formed in its surface. The recess has a bottom forming a second surface with the wall of the recess extending between the first and second surfaces. A source region is formed at the first surface and a drain is formed at the second surface spaced apart from the wall. A channel region is defined along the wall and the second surface between the drain region and the source region. A gate insulator and gate electrode overlie the channel region.

Abstract: A DRAM has a memory cell array in which a plurality of word lines (WL) and a plurality of bit lines (B0) are arranged to orthogonally intersect each other. Memory cells (MC) are arranged in a direction intersecting the bit lines. Capacitors (10) of the memory cells are arranged between the adjacent bit lines. On a silicon substrate (20), the bit line is formed substantially at the same height with the word line and positioned lower than the top of the capacitor. An opening region (15) is formed so that electrode layers (11, 13) of the capacitor do not cover the bit line. The arrangement of the capacitors between the adjacent bit lines allows reduction in the inter-bit-line capacitance. In addition, formation of the region above the bit line which is not covered by the electrode layers of the capacitor makes it possible to reduce the stray capacitance between the capacitor and the bit line.

Abstract: An MOS transistor having a closed layout plan in which the drain is laterally surrounded by the source and gate and having an extended charge carrier drift zone between the gate and drain, thereby achieving high reverse breakdown voltage. An oxide or other dielectric layer is provided on the surface of the drift zone, and on such layer between the gate and drain electrodes a crossover path is formed by a succession of unconnected narrow conductive strips extending transversely to such path and having a dielectric coating thereon. A high voltage external connection bus for the drain electrode traverses such crossover path and extends through a gap formed by a disjuncture in the gate and source electrodes. Since the length of each of the conductive strips greatly exceeds the width of the connection bus, the coupling capacitance between each strip and such bus in much less than the coupling capacitance between such strip and the underlying portion of the drift zone.

Abstract: A semiconductor device includes a semiconductor substrate as a drain region. A metal source region is located on a first surface of the substrate. The metal and the substrate constitute a Schottky junction. An insulated gate, including a gate electrode and an insulating film surrounding the gate electrode, is adjacent to the Schottky junction, such that angle formed by the Schottky junction and the insulated gate in the substrate is an acute angle. A part of the Schottky metal can be buried in the form of a pillar in the substrate, and a channel region of the Schottky junction can be formed on the pillar near the insulated gate.

Abstract: In certain circuits, it is desirable to match the electrical characteristics, (e.g., thresholds), of two (or more) MOS transistors. For example, in an ECL output buffer, a first transistor is a voltage reference, and a second transistor is an output buffer controlled by this voltage reference. However, the orientation of the transistors may affect their electrical characteristics. This may be due to the source/drain ion implantation step that occurs at an angle off the vertical, or other processing effects. The present invention provides symmetrical MOS transistors having characteristics that are independent of orientation. For example, a square gate layout provides both vertical and horizontal current components, thereby obtaining 90 degree rotational symmetry.

Abstract: A multiple quantum well device having a wide well and a plurality of narrower wells spaced from each other and sandwiched between a plurality of barriers and with quantum coupling existing between the wells. Semiconductor substrates and optimal well and barrier widths are selected to yield band gaps and charge localization within the wells such that the energy differences between the ground state of the wide well and the N excited states of the narrow wells correspond to the energy of a photon in the desired spectral range.